A 192MHz to1.946GHz Programmable DLL-Based Frequency Multiplier for RF Applications

A delay-locked loop based frequency multiplier is presented using tsmc 0.18 mum CMOS process parameters. The multiplication factor N can be chosen as an integral number whereas the output frequency range is from 192 MHz to 1.946 GHz. The total power consumption is less than 5.8 mW with a 1.8 V supply. The locking time of the DLL core is 0.66 mus at 250 MHz. The cycle-to-cycle jitter of the DLL core is 46 ps.

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