A low-power CMOS analog vector quantizer

We present a parallel analog vector quantizer (VQ) in 2.0-/spl mu/m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16/spl times/16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell including dynamic template storage measures 60/spl times/78 /spl mu/m/sup 2/. The output code is produced by a 16-cell winner-take-all (WTA) output circuit of linear complexity which selects the winning template with constant power-decay product, independent of input levels and scale. Experimental results demonstrate 34 dB analog input dynamic range and 0.7 mW power dissipation at 3 /spl mu/s cycle.

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