Resilience of ultra-thin oxynitride films to percolative wear-out and reliability implications for high-κ stacks at low voltage stress

Localized progressive wear-out and degradation of ultra-thin dielectrics around the oxygen vacancy percolation path formed during accelerated time dependent dielectric breakdown tests is a well-known phenomenon documented for silicon oxynitride (SiON) based gate stacks in metal oxide semiconductor field effect transistors. This progressive or post breakdown stage involves an initial phase characterized by “digital” random telegraph noise fluctuations followed by the wear-out of the percolation path, which results in an “analog” increase in the leakage current, culminating in a thermal runaway and hard breakdown. The relative contribution of the digital and analog phases of degradation at very low voltage stress in ultra-thin SiON (16 A´) is yet to be fully investigated, which represents the core of this study. We investigate the wear-out process by combining electrical and physical analysis evidences with modeling and simulation results using Kinetic Monte Carlo defect generation and multi-phonon trap ass...

[1]  L. Larcher,et al.  Microscopic Modeling of Electrical Stress-Induced Breakdown in Poly-Crystalline Hafnium Oxide Dielectrics , 2013, IEEE Transactions on Electron Devices.

[2]  Barry P. Linder,et al.  The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability , 2009, 2009 IEEE International Reliability Physics Symposium.

[3]  X. Wu,et al.  Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[4]  Kin Leong Pey,et al.  The physical origin of random telegraph noise after dielectric breakdown , 2009 .

[5]  G. Bersuker,et al.  Role of Interfacial Layer on Breakdown of TiN /High- κ Gate Stacks , 2007 .

[6]  S. Mittl,et al.  Post-breakdown statistics and acceleration characteristics in high-K dielectric stacks , 2011, 2011 International Reliability Physics Symposium.

[7]  J. Sune,et al.  Statistics of successive breakdown events in gate oxides , 2003, IEEE Electron Device Letters.

[8]  Luca Larcher,et al.  Statistical simulation of leakage currents in MOS and flash memory devices with a new multiphonon trap-assisted tunneling model , 2003 .

[9]  K. Shepard,et al.  Analysis of Random Telegraph Noise in 45-nm CMOS Using On-Chip Characterization System , 2013, IEEE Transactions on Electron Devices.

[10]  Barry P. Linder,et al.  Statistics of progressive breakdown in ultra-thin Oxides , 2004 .

[11]  X. Li,et al.  The chemistry of gate dielectric breakdown , 2008, 2008 IEEE International Electron Devices Meeting.

[12]  C.H. Tung,et al.  Multiple Digital Breakdowns and Its Consequence on Ultrathin Gate Dielectrics Reliability Prediction , 2007, 2007 IEEE International Electron Devices Meeting.

[13]  L. Larcher,et al.  A Physical Model for Post-Breakdown Digital Gate Current Noise , 2010, IEEE Electron Device Letters.

[14]  J. McPherson,et al.  UNDERLYING PHYSICS OF THE THERMOCHEMICAL E MODEL IN DESCRIBING LOW-FIELD TIME-DEPENDENT DIELECTRIC BREAKDOWN IN SIO2 THIN FILMS , 1998 .

[15]  E. Wu,et al.  On the progressive breakdown statistical distribution and its voltage acceleration , 2007, 2007 IEEE International Electron Devices Meeting.

[16]  W. B. Knowlton,et al.  A Physical Model of the Temperature Dependence of the Current Through $\hbox{SiO}_{2}\hbox{/}\hbox{HfO}_{2}$ Stacks , 2011, IEEE Transactions on Electron Devices.

[17]  L. Larcher,et al.  The “buffering” role of high-к in post breakdown degradation immunity of advanced dual layer dielectric gate stacks , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[18]  Salvatore Lombardo,et al.  Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient , 2003 .

[19]  M. Kimura Field and temperature acceleration model for time-dependent dielectric breakdown , 1999 .

[20]  Byoung Hun Lee,et al.  Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress , 2006, IEEE Transactions on Device and Materials Reliability.

[21]  L. Larcher,et al.  A physics-based model of the dielectric breakdown in HfO2 for statistical reliability prediction , 2011, 2011 International Reliability Physics Symposium.

[23]  Marc Porti,et al.  Reliability of SiO2 and high-k gate insulators: A nanoscale study with conductive atomic force microscopy , 2007 .

[24]  K. Pey,et al.  A Critical Gate Voltage Triggering Irreversible Gate Dielectric Degradation , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[25]  J. McPherson,et al.  Trends in the ultimate breakdown strength of high dielectric-constant materials , 2003 .

[26]  Kenneth Wu,et al.  Critical gate voltage and digital breakdown: Extending post-breakdown reliability margin in ultrathin gate dielectric with thickness ≪ 1.6 nm , 2009, IEEE International Reliability Physics Symposium.

[27]  G. Groeseneken,et al.  A New TDDB Reliability Prediction Methodology Accounting for Multiple SBD and Wear Out , 2009, IEEE Transactions on Electron Devices.

[28]  Nagarajan Raghavan,et al.  Identifying the First Layer to Fail in Dual-Layer ${\rm SiO}_{\rm x}/{\rm HfSiON}$ Gate Dielectric Stacks , 2013, IEEE Electron Device Letters.

[29]  Patrick M. Lenahan,et al.  The effect of interfacial layer properties on the performance of Hf-based gate stack devices , 2006 .

[30]  J.S. Suehle,et al.  Acceleration factors and mechanistic study of progressive breakdown in small area ultra-thin gate oxides , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[31]  M. Rafik,et al.  High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path , 2010, 2010 IEEE International Reliability Physics Symposium.

[32]  Michel Houssa,et al.  High-? Gate Dielectrics , 2004 .

[33]  SiO2 interfacial layer as the origin of the breakdown of high-k dielectrics stacks , 2008 .

[34]  Guido Groeseneken,et al.  Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications , 2001 .