Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

Technology scaling challenges the effectiveness of current-based test techniques such as I/sub DDQ/. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I/sub DDQ/ versus F/sub MAX/ (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I/sub DDQ/ versus temperature test can be deployed. Our data show that temperature (cooling from 110/spl deg/C to room) improved sensitivity of I/sub DDQ/ versus F/sub MAX/ two-parameter test by more than an order of magnitude (13.8/spl times/). The sensitivity can also be tuned by proper selection of a temperature range to match a required defect per million (DPM) level.

[1]  H. Mizuno,et al.  A 18 /spl mu/A-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[2]  Wojciech Maly,et al.  Current signatures: application , 1997, Proceedings International Test Conference 1997.

[3]  Kaushik Roy,et al.  Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[4]  Manoj Sachdev.  Deep sub-micron I/sub DDQ/ testing: issues and solutions , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[5]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[6]  Wayne M. Needham,et al.  High volume microprocessor test escapes, an analysis of defects our tests are missing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Anthony C. Miller.  I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[8]  Peter Janssen,et al.  Transient current testing of 0.25 /spl mu/m CMOS devices , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[9]  GADI SINGER.  The Future of Test and DFT , 1997, IEEE Des. Test Comput..

[10]  Kaushik Roy,et al.  Intrinsic leakage in low power deep submicron CMOS ICs , 1997, Proceedings International Test Conference 1997.

[11]  Claude Thibeault.  An histogram based procedure for current testing of active defects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[12]  P. Bai,et al.  A high performance 180 nm generation logic technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[13]  Antoni Ferré,et al.  I/sub DDQ/ characterization in submicron CMOS , 1997, Proceedings International Test Conference 1997.

[14]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[15]  Kenneth M. Butler,et al.  So what is an optimal test mix? A discussion of the SEMATECH methods experiment , 1997, Proceedings International Test Conference 1997.

[16]  Peter Janssen,et al.  Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[17]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[18]  T. Ghani,et al.  A high performance 0.25 /spl mu/m logic technology optimized for 1.8 V operation , 1996, International Electron Devices Meeting. Technical Digest.