Advanced Multicore Systems-On-Chip
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[1] Morten Sleth Rasmussen. Network-on-Chip in Digital Hearing Aids , 2006 .
[2] T. Kaneko,et al. Wavelength trimming of a microring resonator filter by means of a UV sensitive polymer overlay , 1999, IEEE Photonics Technology Letters.
[3] Luca P. Carloni,et al. Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Jiang Xu,et al. On the Impact of Crosstalk Noise in Optical Networks-on-Chip , 2014 .
[5] Luca P. Carloni,et al. Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.
[6] Radu Marculescu,et al. "It's a small world after all": NoC performance optimization via long-range link insertion , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Gabriela Nicolescu,et al. Photonic Interconnects for Computing Systems , 2017 .
[8] J.W. Joyner,et al. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC) , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[9] Luca P. Carloni,et al. On the Design of a Photonic Network-on-Chip , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[10] John Keane,et al. An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation , 2010, IEEE Trans. Very Large Scale Integr. Syst..
[11] Michal Lipson,et al. Performance guidelines for WDM interconnects based on silicon microring resonators , 2011, CLEO: 2011 - Laser Science to Photonic Applications.
[12] Eby G. Friedman,et al. 3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[13] Masahiro Sowa,et al. Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization , 2006 .
[14] Axel Jantsch,et al. Methods for fault tolerance in networks-on-chip , 2013, CSUR.
[15] Ho-Young Kim,et al. Top-Down Retargetable Fraemwork with Token-Level Design for Accelerating Simulation Speed of Processor Architecture , 2003 .
[16] Akram Ben Ahmed,et al. Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC , 2010, 2010 International Conference on Broadband, Wireless Computing, Communication and Applications.
[17] Michal Lipson,et al. All-optical switching on a silicon chip. , 2004, Optics letters.
[18] Simon W. Moore,et al. Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[19] Luca Benini,et al. Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.
[20] Andrew B. Kahng,et al. ORION 2.0: A Power-Area Simulator for Interconnection Networks , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[21] Ian O'Connor,et al. Heterogeneous modelling of an optical network-on-chip with SystemC , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).
[22] Xingjun Wang,et al. Reliability considerations of high speed germanium waveguide photodetectors , 2014, OPTO.
[23] Abderazek Ben Abdallah,et al. Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA , 2009 .
[24] R. C. Tiberio,et al. Temperature tuning of microcavity ring and disk resonators at 1.5-/spl mu/m , 1997, Conference Proceedings. LEOS '97. 10th Annual Meeting IEEE Lasers and Electro-Optics Society 1997 Annual Meeting.
[25] Niraj K. Jha,et al. Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.
[26] Biswanath Mukherjee,et al. Fault management in IP-over-WDM networks: WDM protection versus IP restoration , 2002, IEEE J. Sel. Areas Commun..
[27] Dean M. Tullsen,et al. Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).
[28] Bill Lin,et al. Design of application-specific 3D Networks-on-Chip architectures , 2008, 2008 IEEE International Conference on Computer Design.
[29] アクラム ベン アメド. High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems , 2015 .
[30] Yuichi Okuyama,et al. Non-blocking electro-optic network-on-chip router for high-throughput and low-power many-core systems , 2015, 2015 World Congress on Information Technology and Computer Applications (WCITCA).
[31] Nikil D. Dutt,et al. Trends in Emerging On-Chip Interconnect Technologies , 2008, IPSJ Trans. Syst. LSI Des. Methodol..
[32] P. Dumon,et al. Silicon microring resonators , 2012 .
[33] H. Schroder,et al. Single-mode glass waveguide platform for DWDM chip-to-chip interconnects , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.
[34] Ben A. Abderazek,et al. Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router , 2015, 2015 IEEE International Conference on Systems, Man, and Cybernetics.
[35] Oliver Chiu-sing Choy,et al. A low-latency NoC router with lookahead bypass , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[36] G. Lo,et al. Vertically Stacked Multilayer Photonics on Bulk Silicon Toward Three-Dimensional Integration , 2016, Journal of Lightwave Technology.
[37] K. Bergman,et al. Photonic interconnection network architectures using wavelength-selective spatial routing for chip-scale communications , 2012, IEEE/OSA Journal of Optical Communications and Networking.
[38] William J. Dally,et al. Flattened Butterfly Topology for On-Chip Networks , 2007, IEEE Comput. Archit. Lett..
[39] Yi Xu,et al. A power-aware adaptive routing scheme for network on a chip , 2007, 2007 7th International Conference on ASIC.
[40] Sudeep Pasricha,et al. Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures , 2015, IEEE Design & Test.
[41] Hiroki Matsutani,et al. Balanced Dimension-Order Routing for k-ary n-cubes , 2009, 2009 International Conference on Parallel Processing Workshops.
[42] Peter Kok Keong Loh,et al. Design of a Vialbe Fault-Tolerant Routing Strategy for Optical-Based Grids , 2003, ISPA.
[43] Rami G. Melhem,et al. Tolerating process variations in nanophotonic on-chip networks , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[44] Sujit Dey,et al. Efficient exploration of the SoC communication architecture design space , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[45] Chita R. Das,et al. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[46] Xiaowen Wu,et al. Holistic comparison of optical routers for chip multiprocessors , 2012, Anti-counterfeiting, Security, and Identification.
[47] Yu Zhang,et al. Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.
[48] Nisha Checka,et al. Technology, performance, and computer-aided design of three-dimensional integrated circuits , 2004, ISPD '04.
[49] Stephen P. Boyd,et al. Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[50] Venkatesh Akella,et al. Resilient microring resonator based photonic networks , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[51] Samar K. Saha,et al. Modeling Process Variability in Scaled CMOS Technology , 2010, IEEE Design & Test of Computers.
[52] Moustafa Mohamed,et al. Silicon Nanophotonics for Many-Core On-Chip Networks , 2013 .
[53] Sudeep Pasricha,et al. Improving crosstalk resilience with wavelength spacing in photonic crossbar-based network-on-chip architectures , 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).
[54] Hamid Sarbazi-Azad,et al. Multicast-Aware Mapping Algorithm for On-chip Networks , 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.
[55] Akram Ben Ahmed,et al. Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures , 2014, J. Parallel Distributed Comput..
[56] An-Yeu Wu,et al. Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[57] Xiang Ling,et al. The design and implementation of arbiters for Network-on-chips , 2010, 2010 2nd International Conference on Industrial and Information Systems.
[58] Mahmut T. Kandemir,et al. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[59] Ben A. Abderazek,et al. Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems , 2015, The Journal of Supercomputing.
[60] Ming Zhang,et al. Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[61] Jung Ho Ahn,et al. Devices and architectures for photonic chip-scale integration , 2009 .
[62] Lionel M. Ni,et al. The Turn Model for Adaptive Routing , 1992, [1992] Proceedings the 19th Annual International Symposium on Computer Architecture.
[63] Partha Pratim Pande,et al. Performance Evaluation for Three-Dimensional Networks-On-Chip , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).
[64] Abderazek Ben Abdallah,et al. PHENIC: silicon photonic 3D-network-on-chip architecture for high-performance Heterogeneous many-core system-on-chip , 2013 .
[65] Santa Barbara,et al. JPEG Image Compression Using an FPGA , 2006 .
[66] Luca P. Carloni,et al. Networks-on-chip in emerging interconnect paradigms: Advantages and challenges , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[67] Yuichi Okuyama,et al. Efficient Router Architecture, Design and Performance Exploration for Many-Core Hybrid Photonic Network-on-Chip (2D-PHENIC) , 2015, 2015 2nd International Conference on Information Science and Control Engineering.
[68] Akram Ben Ahmed,et al. Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC) , 2013, The Journal of Supercomputing.
[69] Luca P. Carloni,et al. Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.
[70] Glenn Leary,et al. Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance , 2010, 2010 23rd International Conference on VLSI Design.
[71] Ben A. Abderazek,et al. Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems , 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.
[72] Akram Ben Ahmed,et al. FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems , 2015, 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip.
[73] Pradheep Khanna Kaliraj,et al. Reliability-performance trade-offs in photonic NOC architectures , 2013 .
[74] Yan Zhang,et al. A Fault-Tolerant Routing Algorithm Design for On-Chip Optical Networks , 2013, 2013 IEEE 32nd International Symposium on Reliable Distributed Systems.
[75] Luca P. Carloni,et al. PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).