Low delay Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes

Abstract In recent years, there has been a growing interest in codes that can correct adjacent bit errors in memories. This is due to the increasing percentage of radiation induced errors that affect multiple cells due to technology scaling. The cells affected by the errors are physically close and in many cases adjacent. This means that in the absence of interleaving, adjacent bits will be likely to be affected by an error. A number of Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to deal with those errors. These codes have a low overhead in terms of number of additional parity check bits compared to Double Error Correction (DEC) codes. A problem is that they can introduce a significant penalty in terms of delay compared to a Single Error Correction (SEC) or a Single Error Correction and Double Error Detection (SEC-DED) code. This is due to the more complex decoding that needs to check approximately twice the number of syndrome patterns. In this paper, low delay SEC-DAEC codes are presented and the parity check matrices for 16, 32 and 64 bit data words are provided. To reduce the delay, a number of techniques are used in the construction of the code and in the implementation of the decoder. The evaluation shows that this results in significant savings compared to existing SEC-DAEC codes. Therefore, the proposed codes can be useful for high speed designs on which adjacent error correction is required.

[1]  Michail Maniatakos,et al.  Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Pedro Reviriego,et al.  Optimizing the Implementation of SEC–DAEC Codes in FPGAs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[4]  Eiji Fujiwara.  Code Design for Dependable Systems: Theory and Practical Applications , 2006 .

[5]  Nobuyasu Kanekawa,et al.  Dependability in Electronic Systems , 2011 .

[6]  Chin-Long Chen,et al.  Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review , 1984, IBM J. Res. Dev..

[7]  M. Y. Hsiao,et al.  A class of optimal minimum odd-weight-column SEC-DED codes , 1970 .

[8]  Salvatore Pontarelli,et al.  A Method to Design SEC-DED-DAEC Codes With Optimized Decoding , 2014, IEEE Transactions on Device and Materials Reliability.

[9]  Pedro Reviriego,et al.  Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes , 2018, Microelectron. Reliab..

[10]  Pedro Reviriego,et al.  An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Pedro Reviriego,et al.  A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Zhu Ming,et al.  New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory , 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

[13]  Pedro Reviriego,et al.  Efficient error detection in Double Error Correction BCH codes for memory applications , 2012, Microelectron. Reliab..

[14]  Salvatore Pontarelli,et al.  MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Nur A. Touba,et al.  Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[16]  Manoj Sachdev,et al.  Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[17]  Sanghyeon Baeg,et al.  SRAM Interleaving Distance Selection With a Soft Error Failure Model , 2009, IEEE Transactions on Nuclear Science.

[18]  Y. Tosaka,et al.  Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAM's , 2000, IEEE Electron Device Letters.

[19]  Manoj Sachdev,et al.  Neutron Radiation Induced Soft Error Rates for an Adjacent-ECC Protected SRAM in 28 nm CMOS , 2016, IEEE Transactions on Nuclear Science.

[20]  Kwang-Ting Cheng,et al.  Error-locality-aware linear coding to correct multi-bit upsets in SRAMs , 2010, 2010 IEEE International Test Conference.