A Density Metric for Semiconductor Technology [Point of View]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances in semiconductor device technologies enable system-level benefits. The proposed metric can be used to gauge advances in future generations of semi-conductor technologies in a holistic way, by accounting for the progress in logic, memory, and packaging/integration technologies simultaneously.

[1]  H-S Philip Wong,et al.  Memory leads the way to better computing. , 2015, Nature nanotechnology.

[2]  Douglas C. H. Yu Wafer level system integration for SiP , 2014, 2014 IEEE International Electron Devices Meeting.

[3]  Don Monroe,et al.  Neuromorphic computing gets ready for the (really) big time , 2014, CACM.

[4]  Anantha Chandrakasan,et al.  Modern microprocessor built from complementary carbon nanotube transistors , 2019, Nature.

[5]  Thomas N. Theis,et al.  The End of Moore's Law: A New Beginning for Information Technology , 2017, Computing in Science & Engineering.

[6]  Mary Wootters,et al.  The N3XT Approach to Energy-Efficient Abundant-Data Computing , 2019, Proceedings of the IEEE.

[7]  Greg Yeric,et al.  Moore's law at 50: Are we planning for retirement? , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[8]  Mark Bohr,et al.  The new era of scaling in an SoC world , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[10]  Hoon Shin,et al.  A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[11]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[12]  S. Datta,et al.  Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.

[13]  Mark Horowitz,et al.  1.1 Computing's energy problem (and what we can do about it) , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).