Dechirp signal polar format imaging algorithm FPGA (Field Programmable Gate Array) realization method

The invention discloses a dechirp signal polar format imaging algorithm FPGA (Field Programmable Gate Array) realization method, which belongs to the field of radar imaging and digital signal processing. The FPGA (Field Programmable Gate Array) is used for realizing bunching SAR (Synthetic Aperture Radar) polar format algorithm (PFA) mainly for processing the dechirp signal. As radar algorithm processing is usually realized according to range direction and azimuth direction, the design adopts a time division multiplexing mode, FPGA resource use is greatly reduced in the condition in which the processing time is not obviously increased, radar parameters are stored in a DDR3, system initialization adopts a mode of loading the parameters from the DDR3 to the FPGA, and in-chip BRAM resources are further saved.