A fast and effective technique for partial scan selection at RT level

In this paper, we present a method for quickly identifying the scan path chain of datapaths. The originality of the method resides in working with both RT and gate-level level descriptions of circuits. The proposed technique results in a very significant reduction on the CPU time required for scan path selection. We investigate also some directions for the incorporation of partial scan methodology within High Level Synthesis for Testability.

[1]  Miron Abramovici,et al.  A Cost-Based Approach to Partial Scan , 1993, 30th ACM/IEEE Design Automation Conference.

[2]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[3]  Bruno Rouzeyre,et al.  Component selection, scheduling and control schemes for high level synthesis , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[4]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Miodrag Potkonjak,et al.  Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application , 1994, Proceedings of IEEE VLSI Test Symposium.

[6]  Vishwani D. Agrawal,et al.  An economical scan design for sequential logic test generation , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.