A low-IF RX two-point /spl Sigma//spl Delta/-modulation TX CMOS single-chip Bluetooth solution

A new low-cost concept for a system-on-chip Bluetooth solution is proposed in this paper. The single chip includes all necessary baseband and RF parts to achieve full Bluetooth functionality and is implemented in a standard 0.25-/spl mu/m CMOS technology. The two-point modulation /spl Sigma//spl Delta/ fractional N phase-locked loop achieves a phase noise of -124 dBc/Hz at 3-MHz offset. The sensitivity of the embedded low-IF receiver is measured to be -82 dBm at a bit error rate of 0.1%. The power supply voltages for the digital and analog parts are internally regulated to 2.65 V. The maximum current consumption of the analog part is 60 mA.

[1]  S. van Waasen,et al.  A fully integrated CMOS frequency synthesizer for Bluetooth , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[2]  M. Steyaert,et al.  A 2-V CMOS cellular transceiver front-end , 2000, IEEE Journal of Solid-State Circuits.

[3]  Asad A. Abidi Direct-conversion radio transceivers for digital communications , 1995 .

[4]  Michiel Steyaert,et al.  A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology , 1995, IEEE J. Solid State Circuits.

[5]  J.P.K. Gilb Bluetooth radio architectures , 2000, 2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096).