Keeper Effect on Nano Scale Silicon Domino Logic Transistors

[1]  Amit Kumar Pandey,et al.  A 1‐bit full adder using CNFET based dual chirality high speed domino logic , 2019, Int. J. Circuit Theory Appl..

[2]  Sandeep Garg,et al.  FDSTDL: Low‐power technique for FinFET domino circuits , 2019, Int. J. Circuit Theory Appl..

[3]  Sandeep Garg,et al.  Very Low Power Domino Logic Circuits Using Carbon Nanotube Field Effect Transistor Technology , 2019, Journal of Nanoelectronics and Optoelectronics.

[4]  Shipra Upadhyay,et al.  Low power, high speed and noise immune wide-OR footless domino circuit using keeper controlled method , 2018, Analog Integrated Circuits and Signal Processing.

[5]  Tarun Kumar Gupta,et al.  Sleep signal controlled footless domino circuit for low leakage current , 2018 .

[6]  T. K. Gupta,et al.  Analysis and design of lector-based dual-Vt domino logic with reduced leakage current , 2017 .

[7]  H. Xue,et al.  Low power-delay-product dynamic CMOS circuit design techniques , 2017 .

[8]  Mohammad Asyaei,et al.  A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology , 2015, Integr..

[9]  Kavita Khare,et al.  Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits , 2013, Circuits Syst. Signal Process..

[10]  Ali Peiravi,et al.  Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Bharadwaj S. Amrutur,et al.  Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Na Gong,et al.  Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits , 2008, Microelectron. J..

[13]  S. Sharroush,et al.  Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper , 2008, 2008 International Conference on Computer and Communication Engineering.

[14]  Magdy A. Bayoumi,et al.  Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Zhiyu Liu,et al.  PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  A. Amirabadi,et al.  Noise tunable clock delayed domino logic using latched keeper , 2007, 2007 Internatonal Conference on Microelectronics.

[17]  Magdy A. Bayoumi,et al.  A Low Power Domino with Differential-Controlled-Keeper , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[18]  N. Tzartzanis,et al.  A Leakage Current Replica Keeper for Dynamic Circuits , 2006, IEEE Journal of Solid-State Circuits.

[19]  Zhiyu Liu,et al.  Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[20]  Zhiyu Liu,et al.  Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current , 2006, Microelectron. J..

[21]  Ali Afzali-Kusha,et al.  Low power and high performance clock delayed domino logic using saturated keeper , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[22]  Eby G. Friedman,et al.  Sleep switch dual threshold Voltage domino logic with reduced standby leakage current , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Lee-Sup Kim,et al.  A clock delayed sleep mode domino logic for wide dynamic OR gate , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

[24]  Atila Alvandpour,et al.  A sub-130-nm conditional keeper technique , 2002, IEEE J. Solid State Circuits.

[25]  Manoj Sachdev,et al.  A leakage tolerant energy efficient wide domino circuit technique , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[26]  Mohamed I. Elmasry,et al.  Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Sung-Mo Kang,et al.  Skew-tolerant high-speed (STHS) domino logic , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[28]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.