Design of a DSL for Converting Rust Programming Language into RTL

Recent research has focused on a large amount of processing such as streaming processing, big data, deep learning and so on. Since the processing time of these processes increases in proportion to the amount of calculation, an arithmetic unit that can increase the speed is required. In this situation, Field Programmable Gate Array (FPGA) has been attracting attention because it can speed up processing and reduce power consumption. However, Hardware Description Language (HDL) such as Verilog used when developing FPGA increases the development time, but also makes it difficult to guarantee memory safety. In this paper, we propose a Register Transfer Level (RTL) designing Domain Specific Language (DSL) for Rust programming language convert to RTL.

[1]  Ieee Standards Board.  IEEE standard verilog hardware description language , 2001 .

[2]  Kizheppatt Vipin,et al.  FPGA Dynamic and Partial Reconfiguration , 2018, ACM Comput. Surv..

[3]  Tsutomu Maruyama,et al.  Performance comparison of FPGA, GPU and CPU in image processing , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[4]  Robert J. Halstead,et al.  High-Level Language Tools for Reconfigurable Computing , 2015, Proceedings of the IEEE.

[5]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[6]  Ming-Ting Sun,et al.  Resource-Efficient FPGA Architecture and Implementation of Hough Transform , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Fatos Xhafa,et al.  Analysis of Node Placement in Wireless Mesh Networks Using Friedman Test: A Comparison Study for Tabu Search and Hill Climbing , 2015, 2015 9th International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing.

[8]  Nachiket Kapre,et al.  Survey of domain-specific languages for FPGA computing , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[9]  Kwok Kee Wei,et al.  A Survey of SQL Language , 1993 .

[10]  Jocelyn Sérot,et al.  Implementing Stream-Processing Applications on FPGAs: A DSL-Based Approach , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[11]  Sung Ho Park,et al.  High-level hardware design of digital comparator with multiple inputs , 2019, Integr..

[12]  Ivar Jacobson,et al.  Unified Modeling Language , 2020, Definitions.

[13]  Douglas Thain,et al.  Reproducibility in Scientific Computing , 2018, ACM Comput. Surv..

[14]  B. Saravanakumaran,et al.  Survey on Optimization Techniques in High Level Synthesis , 2012 .

[15]  Miguel A. Vega-Rodríguez,et al.  Accelerating floating-point fitness functions in evolutionary algorithms: a FPGA-CPU-GPU performance comparison , 2011, Genetic Programming and Evolvable Machines.

[16]  John Wawrzynek,et al.  Chisel: Constructing hardware in a Scala embedded language , 2012, DAC Design Automation Conference 2012.

[17]  Felix S. Klock,et al.  The rust language , 2014 .

[18]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..

[19]  Kentaro Sano.  DSL-based Design Space Exploration for Temporal and Spatial Parallelism of Custom Stream Computing , 2015, ArXiv.