Reliability correlation between physical and virtual cores at the ISA level

The proliferation of highly-configurable FPGA technology has allowed the implementation of dedicated systems of diverse configurations and fueled the software to hardware migration paradigm. This work demonstrates how the hardware implementation of virtualization technology affects the system reliability at several levels of abstraction. By correlating faults between the physical and virtual, the reliability impact of hardware-assisted virtualization is shown, as well as how runtime faults are capable of breaching virtualization. ISA profiling is used to assess reliability at early design stages and how its use can serve as a robustness guideline for hardware and software designers is explained.

[1]  Young-Jin Kim,et al.  A Flexible and Complexity-Aware H/W Design with SystemC Using Integrated Prototyping , 2009, Proceedings of the 4th International Conference on Ubiquitous Information Technologies & Applications.

[2]  Vassilios A. Chouliaras,et al.  Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor , 2007, IEEE Transactions on Computers.

[3]  Lui Sha,et al.  ORTEGA: An Efficient and Flexible Online Fault Tolerance Architecture for Real-Time Control Systems , 2008, IEEE Transactions on Industrial Informatics.

[4]  Frank Reichenbach,et al.  Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications? , 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

[5]  David R. Kaeli,et al.  Eliminating microarchitectural dependency from Architectural Vulnerability , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[6]  Meeta Sharma Gupta,et al.  Error Tolerance in Server Class Processors , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Ann Gordon-Ross,et al.  A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[8]  Massimo Violante,et al.  Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs , 2011, IEEE Transactions on Industrial Electronics.

[9]  Mahdi Fazeli,et al.  Robust Register Caching: An Energy-Efficient Circuit-Level Technique to Combat Soft Errors in Embedded Processors , 2010, IEEE Transactions on Device and Materials Reliability.

[10]  Daniel M. Russell,et al.  Model-driven development within a legacy system: an industry experience report , 2005, 2005 Australian Software Engineering Conference.

[11]  Francisco J. Cazorla,et al.  Towards improved survivability in safety-critical systems , 2011, 2011 IEEE 17th International On-Line Testing Symposium.

[12]  Todd M. Austin,et al.  A fault tolerant approach to microprocessor design , 2001, 2001 International Conference on Dependable Systems and Networks.

[13]  Peter J. Ashenden,et al.  Programming models for hybrid FPGA-cpu computational components: a missing link , 2004, IEEE Micro.

[14]  David I. August,et al.  Automatic Instruction-Level Software-Only Recovery , 2006, IEEE Micro.

[15]  Oksana Nikiforova,et al.  Discussing the Difference between Model Driven Architecture and Model Driven Development in the Context of Supporting Tools , 2009, 2009 Fourth International Conference on Software Engineering Advances.

[16]  Shubhendu S. Mukherjee,et al.  Measuring Architectural Vulnerability Factors , 2003, IEEE Micro.

[17]  Tatsuo Nakajima,et al.  Composition Kernel: A Multi-core Processor Virtualization Layer for Highly Functional Embedded Systems , 2010, 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing.

[18]  Lui Sha,et al.  ORTEGA: An Efficient and Flexible Software Fault Tolerance Architecture for Real-Time Control Systems , 2008, 2008 Euromicro Conference on Real-Time Systems.

[19]  Gernot Heiser,et al.  Virtualizing embedded systems - why bother? , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[20]  Jonathan Schaeffer,et al.  Generative design patterns , 2002, Proceedings 17th IEEE International Conference on Automated Software Engineering,.

[21]  Stewart Tansley Trends in Embedded Systems--A Microsoft Perspective , 2007, 2007 IEEE International Conference on Microelectronic Systems Education (MSE'07).

[22]  Parimal Patel,et al.  Embedded Systems Design Using FPGA , 2006, VLSI Design.