A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations
暂无分享,去创建一个
[1] Stamatis Vassiliadis,et al. A General Proof for Overlapped Multiple-Bit Scanning Multiplications , 1989, IEEE Trans. Computers.
[2] Louis P. Rubinfield. A Proof of the Modified Booth's Algorithm for Multiplication , 1975, IEEE Transactions on Computers.
[3] M. Hatamian,et al. A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS , 1986 .
[4] O. L. Macsorley. High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.
[5] Andrew D. Booth,et al. A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .
[6] Kai Hwang,et al. Computer arithmetic: Principles, architecture, and design , 1979 .
[7] Ramautar Sharma,et al. A Technology Independent MOS Multiplier Generator , 1984, 21st Design Automation Conference Proceedings.
[8] Joseph Cavanagh,et al. Digital Computer Arithmetic , 1983 .
[9] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..