Temperature effect on delay for low voltage applications [CMOS ICs]

This paper presents one of the first analysis of the temperature dependence of CMOS integrated circuit delay at low voltage. Based on a low voltage extended Sakurai's /spl alpha/-power current law, a detail analysis of the temperature and voltage sensitivity of CMOS structure delay is given. Coupling effects between temperature and voltage are clearly demonstrated. Specific derating factors are defined for the low voltage range (1-3 V/sub TO/). Experimental validations are obtained on specific ring oscillators integrated on a 0.7 /spl mu/m process by comparing the temperature and voltage evolution of the measured oscillation period to the calculated ones. A low temperature sensitivity operating region has been clearly identified and appears in excellent agreement with the expected calculated values.

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