Rapid Calibration of DAC and Gain Errors in a Multi-bit Pipeline Stage

A 11-bit 45MS/s pipelined ADC with rapid background calibration of both DAC and gain errors is described. A dual ADC technique is used to achieve calibration within only 104 clock cycles - several orders of magnitude faster than prior state of the art. Measured results from a prototype in a 1.8V, 0.18μm CMOS process show calibration to improve the peak INL of the ADC from 6.4 LSB to 1.1 LSB.