On the Detectability of Scan Chain Internal Faults An Industrial Case Study

Scan chains contain approximately 50% of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by scan tests and assumed detected by flush tests. Reported results of targeting the scan cell internal faults using checking sequences show such tests to be about 4.5 times longer than scan stuck-at test sets and require a sequential test generator, even for full scan circuits. We present the first step in developing an alternative test methodology for scan cell internal faults. Fault detection capability of existing tests (flush tests, stuck-at tests and transition delay fault tests) are quantified. Existing tests are shown to have similar coverage as checking sequences. A new flush test, viz. half-speed flush test, is defined. This new test is shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault coverage, respectively.

[1]  C. Aissi,et al.  Design and implementation of a fully testable CMOS D-latch , 1995, Proceedings of 5th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[2]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[3]  Edward J. McCluskey,et al.  Checking experiments to test latches , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[4]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[5]  Sudhakar Reddy,et al.  Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops , 1986, IEEE Design & Test of Computers.

[6]  Samy Makar Checking Experiments for Scan Chain Lathes and Flip-FLops , 1997 .

[7]  Edward J. McCluskey,et al.  ATPG for scan chain latches and flip-flops , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[8]  Melvin A. Breuer,et al.  A Universal Test Sequence for CMOS Scan , 1990 .

[9]  Edward J. McCluskey,et al.  Functional tests for scan chain latches , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[10]  S.R. Makar,et al.  Iddq test pattern generation for scan chain latches and flip-flops , 1997, Digest of Papers IEEE International Workshop on IDDQ Testing.