QsNetII: An interconnect for supercomputing applica-tions

The QsNet II network has been designed to optimize the interprocessor communication performance in systems constructed from standard server building blocks. In order to achieve this, the network interface incorporates a number of innovative features, to minimise latency for short messages, and achieve the maximum bandwidth from a standard PCI-X interface. The network interface has a full 64 bit virtual addressing capability and can perform RDMA operation from user space to user space in 64 bit architectures. An embedded I/O processor, which is user programmable, can be used to offload asynchronous protocol handling tasks. The resulting system offers the highest MPI performance available on systems based on standard processing nodes.