论文信息 - PERFORMANCE EVALUATION OF PROPOSED VEDIC MULTIPLIER IN MICROWIND

PERFORMANCE EVALUATION OF PROPOSED VEDIC MULTIPLIER IN MICROWIND

In this paper, we have designed 4* 4 bit multipliers, Braun array multiplier, CSA multiplier, and proposed, Vedic multiplier. The multiplier circuits are designed using DSCH2 VLSI CAD tools and their layouts are generated by Microwind 3 VLSI CAD tools. The output parameters such as propagation delay, total chip area, throughtput, Latency and power dissipation are calculated by using BSIM4 model in Microwind. The simulated results of the three multipliers are compared. From the analysis of these simulated results, it was found that the proposed Vedic multiplier circuit gives better performance.

B. P. Patil | Prabha S. Kasliwal

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