AES Datapaths on FPGAs: A State of the Art Analysis

Since the establishment of the Advanced Encryption Standard (AES), several industrial and academic contributions have been presented towards its improvement focusing on different requirements. The typical restrictions considered in the state of the art are speed, resource efficiency, and compactness. Within the several existing technologies, FPGAs have gained a big market share due to their high adaptability, decreasing cost, and ease to prototype and low time to market. Within FPGA technology, several variations of AES datapaths have been proposed since 2001, differentiating themselves in the datapath bit-width, pipeline staging, Key Scheduling approaches, and round rolling/unrolling. More dedicated solutions have also been proposed for each of the AES operations, considering the use of BRAMs and DSPs, allowing to improve the implementations alongside the inherent evolution of FPGA technologies. This chapter comprises and presents a comprehensive study of state of art AES implementations on FPGA, including a detailed presentation of the AES algorithm and a discussion of the most influential and the most recent architectures proposed to date, providing readers with an updated common ground for future research.

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