Hardware performance of the AES finalists-survey and analysis of results

[1]  Bryan Weeks,et al.  Hardware Performance Simulations of Round 2 Advanced Encryption Standard Algorithms , 2000, AES Candidate Conference.

[2]  Viktor Fischer.  Realization of the Round 2 AES Candidates using Altera FPGA , 2000 .

[3]  Kris Gaj,et al.  Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays , 2001, CT-RSA.

[4]  John Wawrzynek,et al.  A Comparison of the AES Candidates Amenability to FPGA Implementation , 2000, AES Candidate Conference.

[5]  Mitsuru Matsui,et al.  Hardware Evaluation of the AES Finalists , 2000, AES Candidate Conference.

[6]  José D. P. Rolim,et al.  A Comparative Study of Performance of AES Final Candidates Using FPGAs , 2000, CHES.

[7]  Piotr BORA,et al.  IMPLEMENTATION OF THE SERPENT ALGORITHM USING ALTERA FPGA DEVICES , 2000 .

[8]  中嶋 純子,et al.  Cryptographic Hardware and Embedded Systems (CHES'99)国際会議参加報告 , 1999 .

[9]  P. Mroczkowski.  Implementation of the block cipher Rijndael using Altera FPGA , 2001 .

[10]  Miles E. Smid.  A Strategy for Analyzing Public Comments and Preparing the Round 2 Status Report , 2000 .

[11]  Karl Gass,et al.  A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond , 1999, CHES.

[12]  Christof Paar,et al.  An FPGA implementation and performance evaluation of the Serpent block cipher , 2000, FPGA '00.

[13]  Christof Paar,et al.  An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists , 2000, AES Candidate Conference.

[14]  Shai Halevi,et al.  MARS - a candidate cipher for AES , 1999 .

[15]  Kris Gaj,et al.  Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware , 2000, AES Candidate Conference.