Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture

This article proposes to explore parallelism in Turbo-Product Code (TPC) decoding through a parallelism level classification and characterization. From this design space exploration, an innovative TPC decoder architecture without any interleaving resource is presented. This architecture includes a fully-parallel SISO decoder capable of processing n symbols in one clock period. Syntheses results show the better efficiency of such an architecture compared with existing solutions. Considering a six-iteration turbo decoder of a BCH(32,26)2 product code, synthesized in 90 nm CMOS technology, 10 Gb/s can be achieved with an area of 600 Kgates. Moreover, a second architecture enhancing parallelism rate is described. The throughput is 50 Gb/s while an area estimation gives 2.2 Mgates. Finally, comparisons with existing TPC decoders and existing LDPC decoders are performed. They validate the potential of proposed TPC decoder for Gb/s optical fiber transmission systems.

[1]  S. Lakshmivarahan,et al.  Parallel Sorting Algorithms , 1984, Adv. Comput..

[2]  Christophe Jégo,et al.  Towards Gb/s turbo decoding of product code onto an FPGA device , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[3]  P. A. Wintz,et al.  Error Free Coding , 1973 .

[4]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[5]  Camille Leroux,et al.  Full-parallel architecture for turbo decoding of product codes , 2006 .

[6]  Keshab K. Parhi,et al.  High speed VLSI architecture design for block turbo decoder , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[7]  Christophe Jégo,et al.  Efficient architecture for Reed Solomon block turbo code , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[8]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[9]  Christophe Jégo,et al.  A highly parallel Turbo Product Code decoder without interleaving resource , 2008, 2008 IEEE Workshop on Signal Processing Systems.

[10]  Christophe Jégo,et al.  High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping , 2009, J. Signal Process. Syst..

[11]  James L. Massey,et al.  Shift-register synthesis and BCH decoding , 1969, IEEE Trans. Inf. Theory.

[12]  Ieee Microwave Theory,et al.  IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed Broadband Wireless Access Systems Draft Amendment: Management Information Base Extensions , 2007 .

[13]  Takashi Mizuochi,et al.  Experimental demonstration of net coding gain of 10.1 dB using 12.4 Gb/s block turbo code with 3-bit soft decision , 2003, OFC 2003 Optical Fiber Communications Conference, 2003..

[14]  Frank R. Kschischang,et al.  A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[15]  Takashi Mizuochi,et al.  Next generation FEC for optical transmission systems , 2003, OFC 2003 Optical Fiber Communications Conference, 2003..

[16]  M. Jezequel,et al.  Exploring Parallel Processing Levels for Convolutional Turbo Decoding , 2006, 2006 2nd International Conference on Information & Communication Technologies.

[17]  Christophe Jégo,et al.  Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design , 2008, EURASIP J. Wirel. Commun. Netw..

[18]  Dennis W. Prather,et al.  2.4 /spl mu/m cutoff wavelength AlGaAsSb/InGaAsSb phototransistors , 2006 .

[19]  Christophe Jégo,et al.  On the higher efficiency of parallel Reed-Solomon turbo-decoding , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[20]  Ramesh Pyndiah,et al.  Near optimum decoding of product codes , 1994, 1994 IEEE GLOBECOM. Communications: The Global Bridge.

[21]  Ramesh Pyndiah,et al.  Performance and complexity of block turbo decoder circuits , 1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems.

[22]  M. Noda,et al.  High throughput hardware architecture for (1440,1344) low-density parity-check code utilizing quasi-cyclic structure , 2008, 2008 5th International Symposium on Turbo Codes and Related Topics.

[23]  Ramesh Pyndiah,et al.  New architecture for high data rate turbo decoding of product codes , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.

[24]  David Chase,et al.  Class of algorithms for decoding block codes with channel measurement information , 1972, IEEE Trans. Inf. Theory.

[25]  G. David Forney,et al.  Generalized minimum distance decoding , 1966, IEEE Trans. Inf. Theory.