9T balanced SRAM cell for low power operation

The increasing market of mobile devices and battery powered portable electronic systems is creating demands for chips that consume the smallest possible amount of power. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing the power consumption during both read and write operations. In this paper, we have proposed a new SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption. The proposed circuit consumes lower power during read and write operations compared to 6T conventional circuit. The main disadvantage of the proposed cell is its larger area occupation. The stability and speed of the cell are deteriorated which can be improved by proper sizing of the tail transistor.

[1]  Massoud Pedram,et al.  Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Ajay Kumar Singh,et al.  A proposed SRAM cell for low power consumption during write operation , 2009 .

[3]  Akira Tada,et al.  Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation , 2008, J. Comput..

[4]  Rajiv V. Joshi,et al.  Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics , 2009, IEEE Journal of Solid-State Circuits.

[5]  S. Natarajan,et al.  A high density, low leakage, 5T SRAM for embedded caches , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[6]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[7]  Lawrence T. Clark,et al.  Leakage Controlled Read Stable Static Random Access Memories , 2008, J. Comput..

[8]  Magdy A. Bayoumi,et al.  Low-Power Cache Design Using 7T SRAM Cell , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[9]  Christian Piguet.  Low-Power Processors and Systems on Chips , 2005 .

[10]  Vasily G. Moshnyaga,et al.  Low-Power Cache Design , 2018, Low-Power Processors and Systems on Chips.

[11]  Feipei Lai,et al.  Zero-aware asymmetric SRAM cell for reducing cache power in writing zero , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Lee-Sup Kim,et al.  A low-power SRAM using hierarchical bit line and local sense amplifiers , 2005, IEEE J. Solid State Circuits.

[13]  Yong-Bin Kim,et al.  A Highly-Stable Nanometer Memory for Low-Power Design , 2008, 2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems.