Peak-SNR Analysis of CMOS TDCs for SPAD-Based TCSPC 3D Imaging Applications

TDCs formed by ring oscillators are arrayable, scalable, and low power, making them suitable for SPAD-based TCSPC 3D imaging systems. The TDC precision affects the ranging accuracy and, hence, the quality of the reconstructed 3D image. This paper studies the jitter of ring-oscillator-based TDCs as a function of their full-scale-range and derives an expression for the TDC total jitter. The introduced behavioral model describes three different regions of the SNR for TDCs. A peak-SNR designpoint is identified. Increasing the full-scale-range of the TDC beyond this point entails increased jitter and, thus, ultimately a declining SNR. The analysis is validated using post-layout simulations of a ring-oscillator-based TDC designed in 65nm CMOS. A TDC resolution degradation factor defines the TDC jitter behavioral model. It is consistent with FOMs that have been used in the past to evaluate TDCs and clarifies their underlying assumptions.

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