Reliability Challenges Related to TSV Integration and 3-D Stacking

This article identifies four major reliability challenges related to TSV-based 3-D integrated circuits and their solutions that are being developed at imec.

[1]  E. Beyne,et al.  Impact of post-plating anneal and through-silicon via dimensions on Cu pumping , 2013, 2013 IEEE 63rd Electronic Components and Technology Conference.

[2]  Pascal Vivet,et al.  Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits , 2016, IEEE Design & Test.

[3]  Eric Beyne,et al.  W2W permanent stacking for 3D system integration , 2014, 2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).

[4]  Bart Vandevelde,et al.  Impact of the electrodeposition chemistry used for TSV filling on the microstructural and thermo-mechanical response of Cu , 2011 .

[5]  Eric Beyne,et al.  Effect of test structure on electromigration characteristics in 3D-TSV stacked devices , 2014 .

[6]  Bart Vandevelde,et al.  Cu pumping in TSVs: Effect of pre-CMP thermal budget , 2011, Microelectron. Reliab..

[7]  E. Beyne,et al.  Impact of through silicon vias on front-end-of-line performance after thermal cycling and thermal storage , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[8]  Eric Beyne,et al.  Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices , 2015 .

[9]  A. Jourdain,et al.  3D stacked IC demonstration using a through Silicon Via First approach , 2008, 2008 IEEE International Electron Devices Meeting.

[10]  G. Beyer,et al.  Impact of 3D integration on 7nm high mobility channel devices operating in the ballistic regime , 2014, 2014 IEEE International Electron Devices Meeting.

[11]  E. Beyne,et al.  3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias , 2006, 2006 International Electron Devices Meeting.

[12]  G. Beyer,et al.  Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology , 2012, 2012 International Electron Devices Meeting.

[13]  Eric Beyne,et al.  300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications , 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

[14]  E. Beyne 3D interconnection and packaging: impending reality or still a dream? , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[15]  K. Croes,et al.  Electrical characterization method to study barrier integrity in 3D through-silicon vias , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[16]  E. Beyne,et al.  Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[17]  E. Beyne,et al.  The underfill-microbump interaction mechanism in 3D ICs: Impact and mitigation of induced stresses , 2014, 2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE).

[18]  Eric Beyne,et al.  Impact of Cu TSVs on BEOL metal and dielectric reliability , 2014, 2014 IEEE International Reliability Physics Symposium.

[19]  E. Beyne,et al.  Impact of barrier integrity on liner reliability in 3D through silicon vias , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[20]  Eric Beyne,et al.  The 3-D Interconnect Technology Landscape , 2016, IEEE Design & Test.

[21]  E. Beyne,et al.  FET arrays as CPI sensors for 3D stacking and packaging characterization , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[22]  Bart Vandevelde,et al.  Thermal mismatch induced reliability issues for Cu filled through-silicon vias , 2012, 2012 4th Electronic System-Integration Technology Conference.

[23]  Eric Beyne,et al.  Reliability study of liner/barrier/seed options for via-middle TSV's with 3 micron diameter and below , 2015, 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).

[24]  J. Safran,et al.  Through silicon via (TSV) effects on devices in close proximity - the role of mobile ion penetration - characterization and mitigation , 2014, 2014 IEEE International Electron Devices Meeting.

[25]  Matthias Petzold,et al.  Innovative Failure Analysis Techniques for 3-D Packaging Developments , 2016, IEEE Design & Test.

[26]  Bart Vandevelde,et al.  Impact of oxide liner properties on TSV Cu pumping and TSV stress , 2015, 2015 IEEE International Reliability Physics Symposium.

[27]  E. Beyne,et al.  Correlation between Cu microstructure and TSV Cu pumping , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[28]  G. Beyer,et al.  Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology , 2013, 2013 IEEE International Electron Devices Meeting.

[29]  Eric Beyne,et al.  Development of underfilling and thermo-compression bonding processes for stacking multi-layer 3D ICs , 2014, Proceedings of the 5th Electronics System-integration Technology Conference (ESTC).

[30]  Bart Vandevelde,et al.  Electromigration failure mechanisms for different flip chip bump configurations , 2011, 2011 International Reliability Physics Symposium.

[31]  E. Beyne,et al.  Effect of TSV presence on FEOL yield and reliability , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).