Chapter 21 – Gigabit Transceivers

Publisher Summary Gigabit transceivers blocks are found prominently in today's high-end field-programmable gate arrays (FPGA). These high-speed serial interfaces use one pair of differential signals to transmit (TX) data and another pair to receive (RX) data. The reason for using differential pairs is that these signals are less susceptible to noise from an external source, such as radio interference or another signal switching in close proximity to these tracks. To illustrate this, the same amount of noise applied to both a single wire and a differential pair have been considered. The gigabit transceiver blocks embedded in FPGAs typically have a number of configurable (programmable) features. Different vendors and device families may support different subsets of these features such as comma detection, differential output swings, on-chip termination resistors, pre-emphasis, and equalization. High-speed serial interfaces are asynchronous in nature. Thus, the receiver portion of the transceiver includes clock and data recovery (CDR) circuitry that keys off the rising and falling edges of the incoming signal and automatically derives a clock that is representative of the incoming data rate.