A fast algorithm for energy-aware mapping of cores onto WK-recursive NoC under performance constraints

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. Mapping an application, which is described by a parameterized task graph, onto NoC is a key research problem in NoC design. In this paper, we first propose an energy-aware cores mapping approach on WK-recursive NoC, and then present a fast clustering-based scheduling algorithm that maps the cores onto WK-recursive NoC architecture under bandwidth constraints to minimize the total communication energy. Experimental results show that the proposed algorithm is able to handle large task graphs and provide near optimal cores mapping in a few seconds on a PC platform.

[1]  Vincenzo Catania,et al.  Multi-objective mapping for mesh-based NoC architectures , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[2]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[3]  A. Raghunathan,et al.  Battery-driven system design: a new frontier in low power design , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[4]  Shashi Kumar,et al.  A two-step genetic algorithm for mapping task graphs to a network on chip architecture , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[5]  Hussein T. Mouftah,et al.  Topological properties of WK-recursive networks , 1990, [1990] Proceedings. Second IEEE Workshop on Future Trends of Distributed Computing Systems.

[6]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[7]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[8]  C. Sanges,et al.  A recursively scalable network VLSI implementation , 1988, Future Gener. Comput. Syst..

[9]  Kurt Keutzer,et al.  A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Suresh Chalasani,et al.  A Framework for Designing Deadlock-Free Wormhole Routing Algorithms , 1996, IEEE Trans. Parallel Distributed Syst..

[11]  L. Benini,et al.  Analysis of power consumption on switch fabrics in network routers , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[12]  Radu Marculescu,et al.  Energy-aware mapping for tile-based NoC architectures under performance constraints , 2003, ASP-DAC '03.

[13]  Tarek A. El-Ghazawi,et al.  Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[14]  Erik B. van der Tol,et al.  Mapping of MPEG-4 decoding on a flexible architecture platform , 2001, IS&T/SPIE Electronic Imaging.

[15]  Dara Rahmati,et al.  A Performance and Power Analysis of WK-Recursive and Mesh Networks for Network-on-Chips , 2006, 2006 International Conference on Computer Design.

[16]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[17]  Luca Benini,et al.  Packetized on-chip interconnect communication analysis for MPSoC , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[18]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.