ESD Simulation using Compact Models: from I/O Cell to Full Chip

The modeling of ESD devices, such as MOS transistors, under ESD stress and bias conditions is reviewed. A practical macro-modeling approach composed of industry standard BJT and MOS compact models is presented. SPICE-type circuit level simulations that uses these models is demonstrated. These include examples at both the I/O cell as well as full-chip levels. Predicting ESD circuit performance as well as the inherent circuit simulation challenges are discussed.

[1]  T. Luk,et al.  Modeling MOS snapback for circuit-level ESD simulation using BSIM3 and VBIC models , 2005, Sixth international symposium on quality electronic design (isqed'05).

[2]  Yuanzhong Zhou,et al.  Modeling snapback of LVTSCR devices for ESD circuit simulation using advanced BJT and MOS models , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[3]  H.C. de Graaff,et al.  Avalanche multiplication in a compact bipolar transistor model for circuit simulation , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[4]  Junjun Li,et al.  Compact modeling of on-chip ESD protection devices using Verilog-A , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  S. Ramaswamy,et al.  Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations , 1996, Proceedings of International Reliability Physics Symposium.

[6]  Chenming Hu,et al.  An analytical breakdown model for short-channel MOSFET's , 1982, IEEE Transactions on Electron Devices.

[7]  G. Groeseneken,et al.  A compact model for the grounded-gate nMOS behaviour under CDM ESD stress , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[8]  Yuanzhong Zhou,et al.  Compact modeling of on-chip ESD protection using standard MOS and BJT models , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

[9]  Wolfgang Fichtner,et al.  Modular approach of a high current MOS compact model for circuit-level ESD simulation including transient gate coupling behavior , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[10]  Sung-Mo Kang,et al.  Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[11]  Yuanzhong Zhou,et al.  Effect of large device capacitance on FICDM peak current , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[12]  Juin J. Liou,et al.  Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..