Compact Verilog-A model of phase-change RAM transient behaviors for multi-level applications

A new phase-change RAM (PCRAM) model is proposed in this paper for multi-level-cell (MLC) applications. The proposed model has been verified to reproduce the electrical behaviors well in various partial states. Moreover, it has been shown that the programming transient behaviors with various quenching times could be estimated using the proposed model. The new unified PCRAM model which describes three different regions of PCRAM with only one equation has three times smaller discrepancy between the model and measurement than the previous piecewise linear model. For the continuity in PCRAM resistance, the new model shows smooth transition at the boundaries between different regions, whereas some abrupt changes in PCRAM resistance were found in the piecewise model. The compactness with the simple parameter extraction, the continuity for the reliable simulation and the accuracy in the negative differential resistance region make the proposed model useful and suitable in developing the future MLC PCRAM circuits.

[1]  Daniele Ielmini,et al.  Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices , 2007 .

[2]  D. Ielmini,et al.  Physics-based analytical model of chalcogenide-based memories for array simulation , 2006, 2006 International Electron Devices Meeting.

[3]  Jin He,et al.  Verilog-A model for phase change memory simulation , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[4]  Sung-Mo Kang,et al.  A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs , 2009, IEICE Electron. Express.

[5]  Byung-Gil Choi,et al.  A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput , 2008, IEEE Journal of Solid-State Circuits.

[6]  K. Gopalakrishnan,et al.  Phase change memory technology , 2010, 1001.1164.

[7]  H.-S. Philip Wong,et al.  Phase Change Memory , 2010, Proceedings of the IEEE.

[8]  Q. Li.  Blend Implicit Shapes using Smooth Unit Step Functions , 2004, WSCG.

[9]  Guido Torelli,et al.  A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage , 2009, IEEE Journal of Solid-State Circuits.

[10]  K. Sonoda,et al.  A Compact Model of Phase-Change Memory Based on Rate Equations of Crystallization and Amorphization , 2008, IEEE Transactions on Electron Devices.

[11]  I-Ru Chen,et al.  Compact Thermal Model for Vertical Nanowire Phase-Change Memory Cells , 2009, IEEE Transactions on Electron Devices.

[12]  Yi-Bo Liao,et al.  Temperature-based phase change memory model for pulsing scheme assessment , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[13]  Yi-Bo Liao,et al.  Phase change memory modeling using Verilog-A , 2007 .

[14]  A. Cabrini,et al.  An integrated multi-physics approach to the modeling of a phase-change memory device , 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

[15]  A. Pirovano,et al.  Analysis of phase distribution in phase-change nonvolatile memories , 2004, IEEE Electron Device Letters.

[16]  D. Ielmini,et al.  Modeling of Programming and Read Performance in Phase-Change Memories—Part I: Cell Optimization and Scaling , 2008, IEEE Transactions on Electron Devices.

[17]  Luping Shi,et al.  Parasitic capacitance effect on programming performance of phase change random access memory devices , 2010 .

[18]  Y.J. Song,et al.  Two-bit cell operation in diode-switch phase change memory cells with 90nm technology , 2008, 2008 Symposium on VLSI Technology.

[19]  C.D. Wright,et al.  Parameterized SPICE model for a phase-change RAM device , 2006, IEEE Transactions on Electron Devices.

[20]  Mansun Chan,et al.  Circuit implementation to describe the physical behavior of phase change memory , 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

[21]  Andrea L. Lacaita,et al.  Switching and programming dynamics in phase-change memory cells , 2005 .

[22]  Byung-Gil Choi,et al.  A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation , 2007, IEEE Journal of Solid-State Circuits.

[23]  Y.C. Chen,et al.  Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory , 2007, 2007 IEEE International Electron Devices Meeting.

[24]  A. Pirovano,et al.  A Phase Change Memory Compact Model for Multilevel Applications , 2007, IEEE Electron Device Letters.

[25]  Melvin P. Shaw,et al.  A thermophonic investigation of threshold and memory switching phenomena in thick amorphous chalcogenide films , 1984 .

[26]  M. Breitwisch,et al.  On the dynamic resistance and reliability of phase change memory , 2008, 2008 Symposium on VLSI Technology.

[27]  X.Q. Wei,et al.  HSPICE macromodel of PCRAM for binary and multilevel storage , 2006, IEEE Transactions on Electron Devices.

[28]  Kyeong-Sik Min,et al.  Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs , 2009, IEICE Electron. Express.

[29]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[30]  W. A. Johnson.  Reaction Kinetics in Processes of Nucleation and Growth , 1939 .

[31]  A. Pirovano,et al.  Scaling analysis of phase-change memory technology , 2003, IEEE International Electron Devices Meeting 2003.