System-level design methodology for streaming multi-processor embedded systems

This dissertation introduces new design methodology for automated design, programming, and implementation of multiprocessor systems-on-chip (MPSoCs) starting at a high level of abstraction. The proposed methodology offers a fully integrated tool-flow for very fast exploration and implementation of alternative MPSoCs, where design space exploration, system-level synthesis, application mapping, and system prototyping of MPSoCs are highly automated. The main idea is starting from a functional specification of an application and a description of an MPSoC at system level, to refine and translate them to lower register transfer level (RTL) descriptions in a systematic and automated way. This is achieved by applying a model-driven approach which exploits the platform-based design concept. In particular, to model an application, we use the Kahn Process Network (KPN) model of computation, which has proved to be well suited for specifying streaming applications in a parallel form. In addition, we have devised a platform model which allows for building MPSoCs in a systematic and automated way that execute KPNs efficiently. We use a mapping model to express the relation between the processes and the communication channels in the application (KPN) and the processing and memory components of the platform.

[1]  Christian Haubelt,et al.  A SystemC-Based Design Methodology for Digital Signal Processing Systems , 2007, EURASIP J. Embed. Syst..

[2]  Andy D. Pimentel,et al.  A systematic approach to exploring embedded system architectures at multiple abstraction levels , 2006, IEEE Transactions on Computers.

[3]  Gerda Janssens,et al.  Multi-dimensional incremental loop fusion for data locality , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[4]  Grant Martin,et al.  Overview of the MPSoC design challenge , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[5]  Vincent Loechner,et al.  Deriving Formulae to Count Solutions to Parameterized Linear Systems using Ehrhart Polynomials: Appl , 1997 .

[6]  Ed F. Deprettere,et al.  Deriving process networks from weakly dynamic applications in system-level design , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[7]  Alexandru Turjan,et al.  Realizations of the Extended Linearization Model , 2002 .

[8]  Vincent Loechner,et al.  Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations , 2004, CASES '04.

[9]  Luciano Lavagno,et al.  Hardware-software co-design of embedded systems: the POLIS approach , 1997 .

[10]  유승주.  Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software , 2001 .

[11]  Paul Feautrier,et al.  Dataflow analysis of array and scalar references , 1991, International Journal of Parallel Programming.

[12]  Ed F. Deprettere,et al.  Compaan: deriving process networks from Matlab for embedded signal processing architectures , 2000, CODES '00.

[13]  K. Keutzer,et al.  System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  Ed F. Deprettere,et al.  Systematic and Automated Multiprocessor System Design, Programming, and Implementation , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Ed F. Deprettere,et al.  Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[16]  Hugo De Man,et al.  Power exploration for data dominated video applications , 1996, ISLPED '96.

[17]  Alberto L. Sangiovanni-Vincentelli,et al.  Benefits and challenges for platform-based design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[18]  Evert-Jan D. Pol,et al.  Design of multi-tasking coprocessor control for Eclipse , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[19]  Damien Lyonnard,et al.  Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Om Prakash Gangwal,et al.  A Heterogeneous Multiprocessor Architecture for Flexible Media Processing , 2002, IEEE Des. Test Comput..

[21]  Gilles Kahn,et al.  Coroutines and Networks of Parallel Processes , 1977, IFIP Congress.

[22]  Kurt Keutzer,et al.  An FPGA-based soft multiprocessor system for IPv4 packet forwarding , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[23]  坂井 利之,et al.  IFIP Congress 74 , 1974 .

[24]  Christian Haubelt,et al.  Efficient Representation and Simulation of Model-Based Designs , 2006, FDL.

[25]  Ed F. Deprettere,et al.  Modeling Stream-Based Applications Using the SBF Model of Computation , 2001, J. VLSI Signal Process..

[26]  Todor Stefanov,et al.  pn: A Tool for Improved Derivation of Process Networks , 2007, EURASIP J. Embed. Syst..

[27]  Pieter van der Wolf,et al.  An MPEG-2 decoder case study as a driver for a system level design methodology , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[28]  E. A. de Kock.  Multiprocessor mapping of process networks: a JPEG decoding case study , 2002 .

[29]  H. De Man,et al.  System-level power exploration for MPEG-2 decoder on embedded cores: a systematic approach , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[30]  Ed F. Deprettere,et al.  Daedalus: Toward composable multimedia MP-SoC design , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[31]  Ahmed Amine Jerraya,et al.  Automatic generation and targeting of application specific operating systems and embedded systems software , 2001, DATE '01.

[32]  Alexandru Turjan,et al.  Translating affine nested-loop programs to process networks , 2004, CASES '04.

[33]  Edward A. Lee,et al.  Dataflow process networks , 1995, Proc. IEEE.

[34]  Neil W. Bergmann,et al.  Performance evaluation of asynchronous logic pipelines with data dependent processing delays , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[35]  Ed F. Deprettere,et al.  Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[36]  Andreas Gerstlauer,et al.  System-level abstraction semantics , 2002, 15th International Symposium on System Synthesis, 2002..

[37]  Ed F. Deprettere,et al.  A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems , 2001, J. VLSI Signal Process..

[38]  Kurt Keutzer,et al.  An automated exploration framework for FPGA-based soft multiprocessor systems , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[39]  Philippe Clauss,et al.  Symbolic Polynomial Maximization Over Convex Sets and Its Application to Memory Requirement Estimation , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[40]  Kees G. W. Goossens,et al.  Guaranteeing the Quality of Services in Networks on Chip , 2003, Networks on Chip.

[41]  Alexandru Turjan,et al.  System design using Khan process networks: the Compaan/Laura approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[42]  Erwin A. de Kock.  Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study , 2002, ISSS.

[43]  Paul Feautrier,et al.  Automatic Parallelization in the Polytope Model , 1996, The Data Parallel Programming Model.

[44]  Amer Baghdadi,et al.  Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[45]  Ed F. Deprettere,et al.  Converting weakly dynamic programs to equivalent process network specifications , 2000 .

[46]  Edward A. Lee,et al.  Ptolemy II, Heterogeneous Concurrent Modeling and Design in JAVA , 2001 .

[47]  Ed F. Deprettere,et al.  System level design with SPADE: an M-JPEG case study , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[48]  D PimentelAndy,et al.  A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels , 2006 .

[49]  Edsger W. Dijkstra,et al.  Selected Writings on Computing: A personal Perspective , 1982, Texts and Monographs in Computer Science.

[50]  Edward A. Lee,et al.  Scheduling dynamic dataflow graphs with bounded memory using the token flow model , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[51]  Yajun Ha,et al.  Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA , 2008, TODE.

[52]  Erwin A. de Kock,et al.  Design and programming of embedded multiprocessors: an interface-centric approach , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[53]  Edward A. Lee,et al.  A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[54]  Ed F. Deprettere,et al.  Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM , 2008, EURASIP J. Embed. Syst..

[55]  P. Feautrier.  Parametric integer programming , 1988 .

[56]  Eric Cheung,et al.  Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip , 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

[57]  Thomas Martyn Parks,et al.  Bounded scheduling of process networks , 1996 .

[58]  Ahmed Amine Jerraya,et al.  Programming models and HW-SW interfaces abstraction for multi-processor SoC , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[59]  Erwin A. de Kock,et al.  YAPI: application modeling for signal processing systems , 2000, Proceedings 37th Design Automation Conference.

[60]  Ralph Johnson,et al.  design patterns elements of reusable object oriented software , 2019 .

[61]  Andy D. Pimentel,et al.  A multiobjective optimization model for exploring multiprocessor mappings of process networks , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

[62]  Ed F. Deprettere,et al.  Laura: Leiden Architecture Research and Exploration Tool , 2003, FPL.

[63]  Ed F. Deprettere,et al.  Exploring Embedded-Systems Architectures with Artemis , 2001, Computer.

[64]  Ed F. Deprettere,et al.  Deriving Process Networks from Nested Loop Algorithms , 2000, Parallel Process. Lett..

[65]  Daniel D. Gajski,et al.  Syntax and Semantics of the SpecC Language , 1997 .

[66]  Alberto L. Sangiovanni-Vincentelli,et al.  Platform-Based Design and Software Design Methodology for Embedded Systems , 2001, IEEE Des. Test Comput..

[67]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[68]  Anshul Kumar,et al.  Automatic synthesis of system on chip multiprocessor architectures for process networks , 2004, CODES+ISSS '04.

[69]  Daniel D. Gajski,et al.  Embedded software generation from system level design languages , 2004 .

[70]  Twan Basten,et al.  Requirements on the Execution of Kahn Process Networks , 2003, ESOP.

[71]  Kees G. W. Goossens,et al.  C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems , 2002, Des. Autom. Embed. Syst..

[72]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[73]  Daniel Gajski,et al.  Embedded software generation from system level design languages , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).