A Fully-Integrated Fractional-N Frequency Synthesizer with VCO Control Voltage Ripple Compensated

This paper proposed an improved fractional-N frequency synthesizer with the VCO control voltage ripple compensated. By adding a tracking feedback loop, it aims to reduce lock time and spurs. The design of fractional-N frequency synthesizer is based on a 180nm CMOS technology with 1.8V supply voltage, with the output frequency range of 699MHz-960MHz and power consumption of 2.504mW. The simulation results show that the frequency-hopping locking time of the proposed frequency synthesizer system is 2us. Compared with the traditional frequency synthesizer, the locking time is reduced by 58%, and voltage ripple is decreased by 51%.

[1]  Michael Peter Kennedy,et al.  Observations and Analysis of Wandering Spurs in MASH-Based Fractional- $N$ Frequency Synthesizers , 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Mostafa Abedi,et al.  A Fast Locking Phase-Locked Loop with Low Reference Spur , 2018, Electrical Engineering (ICEE), Iranian Conference on.

[3]  Fatima T. Almutairi,et al.  Fast-lock phase-locked loop with adaptive controller in 0.18-μm CMOS , 2016, 2016 5th International Conference on Electronic Devices, Systems and Applications (ICEDSA).

[4]  Michael Peter Kennedy.  Nonlinearity-Induced Spurs in Fractional-$N$ Frequency Synthesizers: State of the Art , 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

[5]  Lee-Sup Kim,et al.  A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  D. Abbott,et al.  An accurate analytical spur model for an integer-N phase-locked loop , 2012, 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012).