Design and evaluation of fine-grained power-gating for embedded microprocessors
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Hiroshi Nakamura | Hideharu Amano | Hiroaki Kobayashi | Kimiyoshi Usami | Masaaki Kondo | Mitaro Namiki | Toshiya Komoda | Ryuichi Sakamoto | Weihan Wang | Jun Tsukamoto | Kensaku Matsunaga | Masaru Kudo | Motoki Wada
[1] Liang Yang,et al. Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[2] Jenq Kuen Lee,et al. Compilers for leakage power reduction , 2006, TODE.
[3] Lokesh Sharma,et al. A 32nm Westmere-EX Xeon® enterprise processor , 2011, 2011 IEEE International Solid-State Circuits Conference.
[4] Jeanine Cook,et al. Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization , 2007, 2007 IEEE International Performance, Computing, and Communications Conference.
[5] Trevor Mudge,et al. MiBench: A free, commercially representative embedded benchmark suite , 2001 .
[6] Pradip Bose,et al. A case for guarded power gating for multi-core processors , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.
[7] Dawei Huang,et al. 3.6GHz 16-core SPARC SoC processor in 28nm , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[8] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[9] Saurabh Dighe,et al. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.
[10] Amano Hideharu,et al. A fine grain dynamic sleep control scheme in MIPS R3000 , 2007 .
[11] Y. N. Srikant,et al. Compiler-assisted leakage energy optimization for clustered VLIW architectures , 2006, EMSOFT '06.
[12] G. Sohi,et al. A static power model for architects , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[13] Toshiya Komoda. Compiler-Directed Fine Grain Power Gating for Leakage Power Reduction in Microprocessor Functional Units , 2012 .
[14] Dawei Huang,et al. A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm , 2014, IEEE Journal of Solid-State Circuits.
[15] Y. Kojima,et al. Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating , 2009, 2009 IEEE Asian Solid-State Circuits Conference.
[16] Mohamed I. Elmasry,et al. Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[17] Narayanan Vijaykrishnan,et al. Adapting instruction level parallelism for optimizing leakage in VLIW architectures , 2003 .
[18] Pradip Bose,et al. Dynamic power gating with quality guarantees , 2009, ISLPED.
[19] Eby G. Friedman,et al. Managing static leakage energy in microprocessor functional units , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[20] T. Mudge,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[21] Hiroshi Nakamura,et al. Geyser-2: The second prototype CPU with fine-grained run-time power gating , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).
[22] Jinson Koppanalil,et al. A 1.6 GHz dual-core ARM Cortex A9 implementation on a low power high-K metal gate 32nm process , 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.
[23] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[24] T. Hattori,et al. Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[25] Pradip Bose,et al. Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[26] Santosh Pande,et al. Optimizing Static Power Dissipation by Functional Units in Superscalar Processors , 2002, CC.
[27] Srinivas Katkoori,et al. A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[28] David Blaauw,et al. Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.