Overcoming Variations in Nanometer-Scale Technologies

Nanometer-scale circuits are fundamentally different from those built in their predecessor technologies in that they are subject to a wide range of new effects that induce on-chip variations. These include effects associated with printing finer geometry features, increased atomic-scale effects, and increased on-chip power densities, and are manifested as variations in process and environmental parameters and as circuit aging effects. The impact of such variations on key circuit performance metrics is quite significant, resulting in parametric variations in the timing and power, and potentially catastrophic failure due to reliability and aging effects. Such problems have led to a revolution in the way that chips are designed in the presence of such uncertainties, both in terms of performance analysis and optimization. This paper presents an overview of the root causes of these variations and approaches for overcoming their effects.

[1]  H. Kufluoglu,et al.  MOSFET degradation due to negative bias temperature instability (NBTI) and hot carrier injection (HCI), and its implications for reliability-aware VLSI design , 2007 .

[2]  Sachin S. Sapatnekar,et al.  Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[3]  Israel Koren,et al.  Simulated Annealing Based Temperature Aware Floorplanning , 2007, J. Low Power Electron..

[4]  Niraj K. Jha,et al.  Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems , 2003, ICCAD 2003.

[5]  Erkki Oja,et al.  Independent component analysis: algorithms and applications , 2000, Neural Networks.

[6]  Sachin S. Sapatnekar,et al.  Current source modeling in the presence of body bias , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[7]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..

[8]  Yung-Huei Lee,et al.  Prediction of Logic Product Failure Due To Thin-Gate Oxide Breakdown , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[9]  David Blaauw,et al.  A statistical approach for full-chip gate-oxide reliability analysis , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Yousef Saad,et al.  Iterative methods for sparse linear systems , 2003 .

[11]  David Blaauw,et al.  Circuit optimization using statistical static timing analysis , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[12]  Hsien-Hsin S. Lee,et al.  Microarchitectural Floorplanning Under Performance and Thermal Tradeoff , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[13]  Rajendran Panda,et al.  Statistical delay computation considering spatial correlations , 2003, ASP-DAC '03.

[14]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[15]  Sachin S. Sapatnekar,et al.  Synthesizing a representative critical path for post-silicon delay prediction , 2009, ISPD '09.

[16]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[17]  R. Baumann Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .

[18]  Kia Bazargan,et al.  Clustering based pruning for statistical criticality computation under process variations , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[19]  C.H. Kim,et al.  Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits , 2007, 2007 IEEE Symposium on VLSI Circuits.

[20]  Sani R. Nassif,et al.  Random walks in a supply network , 2003, DAC '03.

[21]  Kai Wang,et al.  On-chip power supply network optimization using multigrid-based technique , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[22]  Pinaki Mazumder,et al.  Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Sani R. Nassif,et al.  A methodology for the simultaneous design of supply and signal networks , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[24]  Trevor Mudge,et al.  Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.

[25]  J.G. Massey,et al.  NBTI: what we know and what we need to know - a tutorial addressing the current understanding and challenges for the future , 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

[26]  Jason Cong,et al.  Thermal-Aware 3D IC Placement Via Transformation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[27]  Kaushik Roy,et al.  Novel sizing algorithm for yield improvement under process variation in nanometer technology , 2004, Proceedings. 41st Design Automation Conference, 2004..

[28]  Sachin S. Sapatnekar,et al.  Incremental solution of power grids using random walks , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[29]  Pingqiang Zhou,et al.  Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors , 2009, 2009 Asia and South Pacific Design Automation Conference.

[30]  Li Shang,et al.  3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[31]  Kevin Skadron,et al.  A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.

[32]  Sachin S. Sapatnekar,et al.  Fast Poisson solvers for thermal analysis , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[33]  Ankur Srivastava,et al.  A general framework for accurate statistical timing analysis considering correlations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[34]  Eric Pop,et al.  Heat Generation and Transport in Nanometer-Scale Transistors , 2006, Proceedings of the IEEE.

[35]  S. Naffziger,et al.  A 90nm variable-frequency clock system for a power-managed Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[36]  Frank Liu,et al.  A General Framework for Spatial Correlation Modeling in VLSI Design , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[37]  Michel R. C. M. Berkelaar,et al.  Gate sizing using a statistical delay model , 2000, DATE '00.

[38]  C. E. Clark The Greatest of a Finite Set of Random Variables , 1961 .

[39]  Jinjun Xiong,et al.  Static timing: Back to our roots , 2008, 2008 Asia and South Pacific Design Automation Conference.

[40]  Jae-Seok Yang,et al.  Stress-driven 3D-IC placement with TSV keep-out zone and regularity study , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[41]  Jason Cong,et al.  A thermal-driven floorplanning algorithm for 3D ICs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[42]  Sachin Sapatnekar,et al.  Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach , 2003, ICCAD 2003.

[43]  Edward J. Nowak,et al.  CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics , 2002, IBM J. Res. Dev..

[44]  Sachin S. Sapatnekar,et al.  Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[45]  Sachin S. Sapatnekar,et al.  Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[46]  Kelin Kuhn,et al.  Managing Process Variation in Intel’s 45nm CMOS Technology , 2008 .

[47]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[48]  Malgorzata Marek-Sadowska,et al.  On-chip power supply network optimization using multigrid-based technique , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[49]  Sachin S. Sapatnekar,et al.  Temperature-Aware Floorplanning of Microarchitecture Blocks with IPC-Power Dependence Modeling and Transient Analysis , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

[50]  Jinjun Xiong,et al.  Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[51]  Sachin S. Sapatnekar,et al.  Thermal via placement in 3D ICs , 2005, ISPD '05.

[52]  Quming Zhou,et al.  Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[53]  Lawrence T. Pileggi,et al.  Asymptotic probability extraction for non-normal distributions of circuit performance , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[54]  Jie Gu,et al.  Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[55]  Sung Kyu Lim,et al.  3D Floorplanning with Thermal Vias , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[56]  S.A. Saller,et al.  Reliability effects on MOS transistors due to hot-carrier injection , 1985, IEEE Transactions on Electron Devices.

[57]  Peter G. Doyle,et al.  Random Walks and Electric Networks: REFERENCES , 1987 .

[58]  David Blaauw,et al.  Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[59]  Wei Shaojun,et al.  Energy-aware supply and body biasing voltage scheduling algorithm , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

[60]  Vladimir Zolotov,et al.  Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[61]  Michael Orshansky,et al.  An efficient algorithm for statistical minimization of total power under timing yield constraints , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[62]  Lawrence T. Pileggi,et al.  Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[63]  Azadeh Davoodi,et al.  Variability Driven Gate Sizing for Binning Yield Optimization , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[64]  Sachin S. Sapatnekar,et al.  A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[65]  Jason Cong,et al.  Thermal-driven multilevel routing for 3-D ICs , 2005, Asia and South Pacific Design Automation Conference.

[66]  Rajendran Panda,et al.  Optimal placement of power-supply pads and pins , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[67]  M. N. Özişik,et al.  Finite Difference Methods in Heat Transfer , 2017 .

[68]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[69]  Sachin S. Sapatnekar,et al.  Placement of 3D ICs with Thermal and Interlayer Via Considerations , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[70]  James H. Stathis,et al.  Reliability limits for the gate insulator in CMOS technology , 2002, IBM J. Res. Dev..

[71]  Jinjun Xiong,et al.  Criticality computation in parameterized statistical timing , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[72]  Srikanth Krishnan,et al.  Impact of negative bias temperature instability on digital circuit reliability , 2005, Microelectron. Reliab..

[73]  Sani R. Nassif,et al.  Power grid analysis using random walks , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[74]  Sachin S. Sapatnekar,et al.  A framework for block-based timing sensitivity analysis , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[75]  Yu Cao,et al.  Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[76]  Sachin S. Sapatnekar,et al.  Prediction of leakage power under process uncertainties , 2007, TODE.

[77]  Sachin S. Sapatnekar,et al.  Partition-driven standard cell thermal placement , 2003, ISPD '03.

[78]  J. Stathis Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits , 2001 .

[79]  Sachin S. Sapatnekar,et al.  High-Efficiency Green Function-Based Thermal Simulation Algorithms , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[80]  Sachin S. Sapatnekar,et al.  An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[81]  Magdy S. Abadir,et al.  Design-Silicon Timing Correlation A Data Mining Perspective , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[82]  Farid N. Najm,et al.  A Linear-Time Approach for Static Timing Analysis Covering All Process Corners , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[83]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[84]  Sachin S. Sapatnekar,et al.  Full-chip analysis of leakage power under process variations, including spatial correlations , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[85]  Sachin S. Sapatnekar,et al.  Temperature-aware routing in 3D ICs , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[86]  Sani R. Nassif,et al.  Power grid reduction based on algebraic multigrid principles , 2003, DAC '03.

[87]  W. Hunter,et al.  AC electromigration characterization and modeling of multilayered interconnects , 1993, 31st Annual Proceedings Reliability Physics 1993.

[88]  T. Sato,et al.  Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[89]  Suk-kyu Ryu,et al.  Thermo-mechanical reliability of 3-D ICs containing through silicon vias , 2009, 2009 59th Electronic Components and Technology Conference.

[90]  S. John,et al.  NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.

[91]  Sachin S. Sapatnekar,et al.  Partition-based algorithm for power grid design using locality , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[92]  J. Black Electromigration failure modes in aluminum metallization for semiconductor devices , 1969 .

[93]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[94]  Sachin S. Sapatnekar,et al.  Congestion-aware topology optimization of structured power/ground networks , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[95]  Yao-Wen Chang,et al.  Joint exploration of architectural and physical design spaces with thermal consideration , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[96]  Vivek De,et al.  Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..

[97]  Sachin S. Sapatnekar,et al.  Statistical timing analysis under spatial correlations , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[98]  Zhi-Quan Luo,et al.  Robust gate sizing by geometric programming , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[99]  Petru Eles,et al.  Overhead-conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[100]  Linda S. Milor,et al.  Reliable cache design with detection of gate oxide breakdown using BIST , 2009, 2009 IEEE International Conference on Computer Design.

[101]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[102]  Sachin S. Sapatnekar,et al.  Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal , 2003, ICCAD 2003.

[103]  S. Naffziger,et al.  Power and temperature control on a 90nm Itanium/sup /spl reg//-family processor , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[104]  Sarma B. K. Vrudhula,et al.  A methodology to improve timing yield in the presence of process variations , 2004, Proceedings. 41st Design Automation Conference, 2004..

[105]  William L. Briggs,et al.  A multigrid tutorial , 1987 .

[106]  David Blaauw,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.

[107]  F. d'Heurle Electromigration and failure in electronics: An introduction , 1971 .

[108]  Sani R. Nassif,et al.  Multigrid-like technique for power grid analysis , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[109]  Sachin S. Sapatnekar,et al.  A hybrid linear equation solver and its application in quadratic placement , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[110]  William L. Briggs,et al.  A multigrid tutorial, Second Edition , 2000 .

[111]  Andrzej J. Strojwas,et al.  Correlation-aware statistical timing analysis with non-Gaussian delay distributions , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[112]  Lawrence T. Pileggi,et al.  Asymptotic Probability Extraction for Nonnormal Performance Distributions , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[113]  Ankur Srivastava,et al.  A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[114]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.

[115]  T. Morimoto,et al.  Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide , 1998 .

[116]  M.A. Alam,et al.  A critical examination of the mechanics of dynamic NBTI for PMOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[117]  Norman C. Beaulieu,et al.  Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications , 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).

[118]  Sachin S. Sapatnekar,et al.  Scalable methods for the analysis and optimization of gate oxide breakdown , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[119]  David Blaauw,et al.  Analysis and minimization techniques for total leakage considering gate oxide leakage , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[120]  C. Kim,et al.  Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits , 2008, IEEE Journal of Solid-State Circuits.

[121]  Tanya Nigam,et al.  Impact of Transistor Level degradation on product reliability , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[122]  Hai Zhou,et al.  Statistical gate sizing for timing yield optimization , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[123]  Noel Menezes,et al.  A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[124]  Sung-Mo Kang,et al.  Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[125]  David Blaauw,et al.  Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[126]  E. Oja,et al.  Independent Component Analysis , 2013 .

[127]  I. Miller Probability, Random Variables, and Stochastic Processes , 1966 .

[128]  William J. Wilson,et al.  Multivariate Statistical Methods , 2005, Technometrics.

[129]  Sani R. Nassif,et al.  Optimal decoupling capacitor sizing and placement for standard-cell layout designs , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[130]  M.S. Abadir,et al.  Refined statistical static timing analysis through learning spatial delay correlations , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[131]  Niraj K. Jha,et al.  Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[132]  V. Reddy,et al.  A comprehensive framework for predictive modeling of negative bias temperature instability , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[133]  Sachin S. Sapatnekar,et al.  NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[134]  P. McLane,et al.  Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications , 1994, International Conference on Communications.

[135]  Sani R. Nassif,et al.  Congestion-driven codesign of power and signal networks , 2002, DAC '02.

[136]  John G. Proakis,et al.  Probability, random variables and stochastic processes , 1985, IEEE Trans. Acoust. Speech Signal Process..

[137]  Peter Hazucha,et al.  Characterization of soft errors caused by single event upsets in CMOS processes , 2004, IEEE Transactions on Dependable and Secure Computing.