A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems
暂无分享,去创建一个
Hiroaki Takada | Hiroyuki Tomiyama | Krzysztof Jozwik | Shinya Honda | H. Tomiyama | S. Honda | H. Takada | Krzysztof Jozwik
[1] Bin Zhang,et al. A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[2] Christian Haubelt,et al. Efficient hardware checkpointing: concepts, overhead analysis, and implementation , 2007, FPGA '07.
[3] Christophe Moy,et al. New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.
[4] Marco Platzner,et al. A Runtime Environment for Reconfigurable Hardware Operating Systems , 2004, FPL.
[5] Jürgen Becker,et al. Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).
[6] Camel Tanougast,et al. A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems , 2007, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
[7] Reinhard Männer,et al. Preemptive multitasking on FPGAs , 2000, Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871).
[8] Heiko Kalte,et al. Context saving and restoring for multitasking in reconfigurable systems , 2005, International Conference on Field Programmable Logic and Applications, 2005..