A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing

In this paper, a computational digital pixel sensor (DPS) equipped with an on-chip image-processing capability has been developed. In order to resolve the interconnection bottleneck between the sensor array and on-chip processing units, a new block-readout architecture has been proposed and implemented on the chip. The data from the sensor array are read out in a form of a pixel block compatible to kernel image processing, and they are processed in parallel by on-chip processing units. Such an architecture has enabled us to carry out an efficient kernel processing using a linear array of single-instruction-multiple-data processing units. In order to demonstrate the advantage of such an architecture, a rank-order filtering circuit has been implemented on the chip as a case study of the on-chip image processing. In this paper, a binary-search rank-order filtering algorithm has been implemented in a simple circuitry. A proof-of-concept chip having an array of 64 times 48 pixels was designed and fabricated using a 0.35-mum CMOS technology, and the concept has been verified by the measuremet of fabricated chips.

[1]  Abbas El Gamal,et al.  A Nyquist rate pixel level ADC for CMOS image sensors , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[2]  Amine Bermak,et al.  A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  A. Bermak,et al.  A novel adaptive logarithmic digital pixel sensor , 2006, IEEE Photonics Technology Letters.

[4]  Robert Henderson,et al.  12.4 SXGA Pinned Photodiode CMOS Image Sensor in 0.35µm Technology , 2003 .

[5]  Tadashi Shibata,et al.  A speed adaptive ego-motion detection system using EDGE-histograms produced by variable graduation method , 2007, 2007 15th European Signal Processing Conference.

[6]  A. El Gamal,et al.  A 640/spl times/512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[7]  A. El Gamal,et al.  CMOS image sensors , 2005, IEEE Circuits and Devices Magazine.

[8]  K. Findlater,et al.  SXGA pinned photodiode CMOS image sensor in 0.35 /spl mu/m technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[9]  L. McIlrath.  A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion , 2001, IEEE J. Solid State Circuits.

[10]  Yoshihiro Fujita,et al.  A digital pixel image sensor for real-time readout , 2000 .

[11]  A. Bermak,et al.  A digital pixel sensor array with programmable dynamic range , 2005, IEEE Transactions on Electron Devices.

[12]  Xinqiao Liu,et al.  A 10000 frames/s CMOS digital pixel sensor , 2001, IEEE J. Solid State Circuits.

[13]  Ari Paasio,et al.  A ranked order filter implementation for parallel analog processing , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[14]  Alejandro Díaz-Sánchez,et al.  A fully parallel CMOS analog median filter , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[15]  Tadashi Shibata,et al.  An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems , 2003, IEEE Trans. Neural Networks.

[16]  K. Ito,et al.  A variable-kernel flash-convolution image filtering processor , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[17]  Wang Yan,et al.  A CMOS Image Sensor with on Chip Image Compression based on Predictive Boundary Adaptation and QTD Algorithm , 2007, 2007 IEEE Sensors.

[18]  Barry Fowler,et al.  A 640×512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC , 1999 .

[19]  Dhiraj K. Pradhan,et al.  A new algorithm for order statistic and sorting , 1993, IEEE Trans. Signal Process..

[20]  Toshihiko Mori,et al.  A Charge-Transfer-Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's , 1997 .

[21]  Eric R. Fossum,et al.  CMOS image sensors: electronic camera on a chip , 1995, Proceedings of International Electron Devices Meeting.

[22]  Tadashi Shibata,et al.  A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[23]  Amine Bermak,et al.  Architecture of a Digital Pixel Sensor Array with Tile-Based Vector Quantization Image Compression Algorithm , 2007, 9th Biennial Conference of the Australian Pattern Recognition Society on Digital Image Computing Techniques and Applications (DICTA 2007).

[24]  B. Fowler,et al.  A CMOS area image sensor with pixel-level A/D conversion , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[25]  Tadashi Shibata,et al.  Validating directional edge-based image feature representations in face recognition by spatial correlation-based clustering , 2007, 2007 15th European Signal Processing Conference.

[26]  Abbas El Gamal,et al.  Pixel-level processing: why, what, and how? , 1999, Electronic Imaging.

[27]  T. Shibata,et al.  A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[28]  Amine Bermak,et al.  A DPS array with programmable resolution and reconfigurable conversion time , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Amine Bermak,et al.  Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[30]  Zhouyuan Shi,et al.  CMOS Digital Pixel Sensor with Multiple Reference, Multiple Sampling Dynamic Range Enhancement , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.