Characterization of FPGA-master ARM communication delays in zynq devices

The Field-Programmable System-on-Chip concept, integrating processors and configurable logic into the same chip, leads to digital design platforms more powerful than processors and FPGAs alone. Efficient communication between the processor and the FPGA fabric is a key factor to achieve maximum performance in these devices. Architectures for processor-FPGA communications include functional blocks like bridges, memories, or interconnect resources, allowing different communication mechanisms to be used, with different design complexity and performance. The main goal of this paper is to characterize the communication delays in Xilinx devices in the cases where the processor acts as communications master. The characterization procedure is the same used in a previous work dealing with Altera devices, with which a comparison is made. This is, to the best of authors' knowledge, the first comparative study between both families of devices. The results show remarkable differences between them.