Novel high-radix residue number system architectures

Novel radix-r modulo-r/sup n/ arithmetic units for residue number system (RNS)-based architectures are introduced in this paper. The proposed circuits are shown to require several times less area than previously reported architectures for particular moduli of operation, while also being preferable in the area/spl times/time complexity sense. The complexity reduction is achieved by extending the carry-ignore property of modulo-2/sup n/ operations to radices higher than two, which are not powers of two. The carry-ignore property is efficiently exploited by introducing simplified digit adders, instead of general radix-r adders. The proposed simplification of digit adders is possible, since the maximum values of certain intermediate digits produced in the architecture are found to be less than r-1. Detailed area and time complexity models are derived for the arithmetic units. The proposed radix-r architectures include multipliers, adders, and merged multipliers-adders. In addition, efficient radix-r binary-to-residue and residue-to-binary conversion techniques and architectures are introduced.

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