The Distribution of Waiting Times in Clocked Multistage Interconnection Networks

Analyzes the random delay experienced by a message traversing a buffered, multistage packet-switching banyan network. The authors find the generating function for the distribution of waiting time at the first stage of the network for a very general class of traffic, assuming messages have discrete sizes. For example, traffic can be uniform or nonuniform, messages can have different sizes, and messages can arrive in batches. For light-to-moderate loads, the authors conjecture that delays experienced at the various stages of the network are nearly the same and are nearly independent. This allows us to approximate the total delay distribution. Better approximations for the distribution of waiting times at later stages of the network are attained by assuming that in the limit a sort of spatial steady state is achieved. Extensive simulations confirm the formulas and conjectures. >

[1]  H. Chernoff,et al.  Central Limit Theorems for Interchangeable Processes , 1958, Canadian Journal of Mathematics.

[2]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[3]  Leonard Kleinrock,et al.  Theory, Volume 1, Queueing Systems , 1975 .

[4]  Hisashi Kobayashi,et al.  Queueing Models for Computer Communications System Analysis , 1977, IEEE Trans. Commun..

[5]  Tse-yun Feng,et al.  A Survey of Interconnection Networks , 1981, Computer.

[6]  Daniel M. Dias,et al.  Packet Switching Interconnection Networks for Modular Systems , 1981, Computer.

[7]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[8]  M. Malek,et al.  Analysis and Simulation of Banyan Interconnection Networks with 2x2, 4x4 and 8x8 Switching Elements , 1982, IEEE Real-Time Systems Symposium.

[9]  Laxmi N. Bhuyan,et al.  An Interference Analysis of Interconnection Networks , 1983, ICPP.

[10]  Ralph Grishman,et al.  The NYU Ultracomputer—Designing an MIMD Shared Memory Parallel Computer , 1983, IEEE Transactions on Computers.

[11]  D. Burman,et al.  Asymptotic analysis of a queueing model with bursty traffic , 1983, The Bell System Technical Journal.

[12]  Marc Snir,et al.  The Performance of Multistage Interconnection Networks for Multiprocessors , 1983, IEEE Transactions on Computers.

[13]  Marc Snir,et al.  On the distribution of delays in buffered multistage interconnection networks for uniform and nonuni , 1984 .

[14]  Gregory F. Pfister,et al.  A Methodology for Predicting Multiprocessor Performance , 1985, International Conference on Parallel Processing.

[15]  Howard Jay Siegel,et al.  Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.) , 1985 .

[16]  Kevin P. McAuliffe,et al.  The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture , 1985, ICPP.