Synthesis of delay fault testable combinational logic
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[1] Sudhakar M. Reddy,et al. On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[2] Kaushik Roy,et al. A Novel Approach to Accurate Timing Verification Using RTL Descriptions , 1989, 26th ACM/IEEE Design Automation Conference.
[3] D. Smith,et al. A Unified Design Representation Can Work , 1989, 26th ACM/IEEE Design Automation Conference.
[4] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[5] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..