Compiler-Directed Fine Grain Power Gating for Leakage Power Reduction in Microprocessor Functional Units

As semiconductor technology scales down, leakage-power becomes dominant in the total power consumption of LSI chips. We propose a compiler technique to turn off functional units that are expected to be idle for long periods of time for reducing leakage-power using fine grain power gating technique. Also, we propose a hybrid technique which combines a compiler and hardware based technique to maximize the chance of power gating. The results of experiments show that our proposed technique can reduce leakage-power of functional units for a wide range of break even time (BET) and applications.

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