Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy

This paper presents SANGRIA, a tool for automated globally reliable variation-aware sizing of analog integrated circuits. Its keys to efficient search are adaptive response surface modeling, and a new concept, structural homotopy. Structural homotopy embeds homotopy-style objective function tightening into the search state's structure, not dynamics. Searches at several different levels are conducted simultaneously: The loosest level does nominal dc simulation, and tighter levels add more analyses and {process, environmental} corners. New randomly generated designs are continually fed into the lowest (cheapest) level, always trying new regions to avoid premature convergence. For further efficiency, SANGRIA adaptively constructs response surface models, from which new candidate designs are optimally chosen according to both yield optimality on model and model prediction uncertainty. The stochastic gradient boosting models support arbitrary nonlinearities, and have linear scaling with input dimension and sample size. SANGRIA uses SPICE in the loop, supports accurate/complex statistical SPICE models, and does not make assumptions about the convexity or differentiability of the objective function. SANGRIA is demonstrated on four different analog circuits having from 10 to 50 devices and up to 444 design/process/environmental variables.

[1]  Kalyanmoy Deb,et al.  A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..

[2]  Michael James Sasena,et al.  Flexibility and efficiency enhancements for constrained global design optimization with kriging approximations. , 2002 .

[3]  Georges G. E. Gielen,et al.  Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[4]  Rob A. Rutenbar,et al.  Techniques and Applications of Symbolic Analysis for Analog Integrated Circuits: A Tutorial Overview , 2002 .

[5]  J. Friedman Stochastic gradient boosting , 2002 .

[6]  H. Graeb,et al.  Mismatch analysis and direct yield optimization by spec-wise linearization and feasibility-guided search , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Rob A. Rutenbar,et al.  Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[8]  Lawrence T. Pileggi,et al.  Asymptotic Probability Extraction for Nonnormal Performance Distributions , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Guido Stehr,et al.  Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier–Motzkin Elimination , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Justin R. Rattner EDA for digital, programmable, multi-radios , 2008, DAC 2008.

[11]  Rob A. Rutenbar,et al.  Practical Synthesis of High-Performance Analog Circuits , 1998 .

[12]  Peng Li,et al.  Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[13]  Robert Hooke,et al.  `` Direct Search'' Solution of Numerical and Statistical Problems , 1961, JACM.

[14]  Helmut Graeb,et al.  Analog Design Centering and Sizing , 2007 .

[15]  Stephen P. Boyd,et al.  ORACLE: optimization with recourse of analog circuits including layout extraction , 2004, Proceedings. 41st Design Automation Conference, 2004..

[16]  Stavros J. Perantonis,et al.  Two highly efficient second-order algorithms for training feedforward networks , 2002, IEEE Trans. Neural Networks.

[17]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Rob A. Rutenbar,et al.  WiCkeD: Analog Circuit Synthesis Incorporating Mismatch , 2002 .

[19]  Robin Sibson,et al.  The Construction of Hierarchic and Non-Hierarchic Classifications , 1968, Comput. J..

[20]  DebK.,et al.  A fast and elitist multiobjective genetic algorithm , 2002 .

[21]  C.C. McAndrew,et al.  A comprehensive MOSFET mismatch model , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[22]  M. Powell The NEWUOA software for unconstrained optimization without derivatives , 2006 .

[23]  Georges G. E. Gielen,et al.  Analog and digital circuit design in 65 nm CMOS: end of the road? , 2005, Design, Automation and Test in Europe.

[24]  Deniz Yuret From Genetic Algorithms to Efficient Optimization , 1994 .

[25]  Kurt Antreich,et al.  Mismatch analysis and direct yield optimization by specwise linearization and feasibility-guided search , 2001, DAC '01.

[26]  Tamara G. Kolda,et al.  Optimization by Direct Search: New Perspectives on Some Classical and Modern Methods , 2003, SIAM Rev..

[27]  E. B. Wilson Probable Inference, the Law of Succession, and Statistical Inference , 1927 .

[28]  Donald R. Jones,et al.  Efficient Global Optimization of Expensive Black-Box Functions , 1998, J. Glob. Optim..

[29]  Stephen P. Boyd,et al.  OPERA: optimization with ellipsoidal uncertainty for robust analog IC design , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[30]  Eric R. Ziegel,et al.  The Elements of Statistical Learning , 2003, Technometrics.

[31]  Rob A. Rutenbar,et al.  Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Richard J. Beckman,et al.  A Comparison of Three Methods for Selecting Values of Input Variables in the Analysis of Output From a Computer Code , 2000, Technometrics.

[33]  Ulf Schlichtmann,et al.  The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[34]  Georges Gielen,et al.  A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits , 2002 .

[35]  D K Smith,et al.  Numerical Optimization , 2001, J. Oper. Res. Soc..

[36]  Gregory Hornby,et al.  ALPS: the age-layered population structure for reducing the problem of premature convergence , 2006, GECCO.

[37]  Georges G. E. Gielen,et al.  HOLMES: capturing the yield-optimized design space boundaries of analog and RF integrated circuits , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[38]  Xin Li,et al.  Robust Analog/RF Circuit Design With Projection-Based Performance Modeling , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.