High volume microprocessor test escapes, an analysis of defects our tests are missing
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[1] Yeoh Eng Hong,et al. The application of novel failure analysis techniques for advanced multi-layered CMOS devices , 1997, Proceedings International Test Conference 1997.
[2] Wayne M. Needham,et al. DFT strategy for Intel microprocessors , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[3] Kenneth M. Butler,et al. So what is an optimal test mix? A discussion of the SEMATECH methods experiment , 1997, Proceedings International Test Conference 1997.
[4] Robert C. Aitken,et al. IDDQ and AC scan: the war against unmodelled defects , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[5] Derek Feltham,et al. Pentium(R) Pro processor design for test and debug , 1997, Proceedings International Test Conference 1997.
[6] Wayne Maurice Needham. Designer's Guide to Testable Asic Devices , 1991 .
[7] Derek Feltham,et al. Pentium Pro Processor Design for Test and Debug , 1998, IEEE Des. Test Comput..
[8] P. Nigh,et al. An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).