Direct Mapping of Low-Latency Asynchronous Controllers From STGs

A method for an automated synthesis of low-latency asynchronous controllers is presented. It is based on a direct mapping approach and starts from an initial specification in the form of a signal transition graph (STG). This STG is split into a device and an environment, which synchronize via a communication net that models wires. The device is represented as a tracker and a bouncer. The tracker follows the state of the environment and provides reference points to the device outputs. The bouncer communicates with the environment and generates output events in response to the input events according to the state of the tracker. This two-level architecture provides an efficient interface to the environment and is convenient for subsequent mapping into a circuit netlist. A set of optimization heuristics is developed to reduce the latency and size of the circuit. As a result of this paper, a software tool called OptiMist has been developed. Its low algorithmic complexity allows large specifications to be synthesized, which is not possible for the tools based on state-space exploration. OptiMist successfully interfaces conventional EDA design flow for simulation, timing analysis, and place-and-route

[1]  Steven M. Nowick,et al.  Automatic synthesis of burst-mode asynchronous controllers , 1993 .

[2]  Josep Carmona.  Structural methods for the synthesis of well-formed concurrent specifications , 2003 .

[3]  Steven M. Nowick,et al.  An introduction to asynchronous circuit design , 1998 .

[4]  Alex Yakovlev,et al.  Clockless circuits and system synthesis , 2005 .

[5]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[6]  Luciano Lavagno,et al.  High-Level Modeling and Design of Asynchronous Interface Logic , 1995, IEEE Des. Test Comput..

[7]  Luciano Lavagno,et al.  Logic Synthesis for Asynchronous Controllers and Interfaces , 2002 .

[8]  Kurt Jensen,et al.  Coloured Petri Nets: Basic Concepts, Analysis Methods and Practical Use. Vol. 2, Analysis Methods , 1992 .

[9]  Rob J. van Glabbeek,et al.  Branching time and abstraction in bisimulation semantics , 1996, JACM.

[10]  Robin Milner,et al.  Communication and concurrency , 1989, PHI Series in computer science.

[11]  Enrique Pastor Llorens.  Structural methods for the synthesis of asynchronous circuits from signal transition graphs , 1996 .

[12]  Luciano Lavagno,et al.  What is the cost of delay insensitivity? , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[13]  Wesley A. Clark.  Macromodular computer systems , 1967, AFIPS '67 (Spring).

[14]  Michael Kishinevsky,et al.  Concurrent hardware : the theory and practice of self-timed design , 1993 .

[15]  Ganesh Gopalakrishnan,et al.  High-level asynchronous system design using the ACK framework , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[16]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[17]  Niraj K. Jha,et al.  MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines , 1999 .

[18]  Alain J. Martin.  Compiling communicating processes into delay-insensitive VLSI circuits , 2005, Distributed Computing.

[19]  Teresa H. Y. Meng,et al.  Synthesis of Timed Asynchronous CircuitsChris , 1993 .

[20]  RENA DAVID,et al.  Modular Design of Asynchronous Circuits Defined by Graphs , 1977, IEEE Transactions on Computers.

[21]  Francesca Rossi,et al.  Contextual nets , 1995, Acta Informatica.

[22]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[23]  Kurt Jensen,et al.  Coloured Petri Nets , 1996, Monographs in Theoretical Computer Science. An EATCS Series.

[24]  David A. Huffman,et al.  The synthesis of sequential switching circuits , 1954 .

[25]  Teresa H. Y. Meng,et al.  Automatic gate-level synthesis of speed-independent circuits , 1992, ICCAD '92.

[26]  Peter A. Beerel,et al.  Average-case technology mapping of asynchronous burst-mode circuits , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Ivan E. Sutherland,et al.  GasP: a minimal FIFO control , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[28]  Alex Yakovlev,et al.  Asynchronous circuit synthesis by direct mapping: interfacing to environment , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[29]  Carl-Johan H. Seger,et al.  Design of Asynchronous Circuits , 1995 .

[30]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[31]  Alain J. Martin.  The limitations to delay-insensitivity in asynchronous circuits , 1990 .

[32]  Kees van Berkel.  Beware the isochronic fork , 1992, Integr..

[33]  Kurt Jensen,et al.  Coloured Petri nets (2nd ed.): basic concepts, analysis methods and practical use: volume 1 , 1996 .

[34]  Alexandre Yakovlev,et al.  Design and analysis of a self-timed duplex communication system , 2004, IEEE Transactions on Computers.

[35]  Jo C. Ebergen,et al.  A formal approach to designing delay-insensitive circuits , 1991, Distributed Computing.

[36]  Victor Varshavsky,et al.  Asynchronous Control Device Design by Net Model Behavior Simulation , 1996, Application and Theory of Petri Nets.

[37]  Luciano Lavagno,et al.  Algorithms for Synthesis and Testing of Asynchronous Circuits , 1993 .

[38]  Wolfgang Reisig,et al.  Informal Introduction to Petri Nets , 1996, Applications and Theory of Petri Nets.

[39]  Theodore M. Booth.  Demonstrating hazards in sequential relay circuits , 1963, SWCT.

[40]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[41]  Lee A. Hollaar.  Direct Implementation of Asynchronous Control Units , 1982, IEEE Transactions on Computers.

[42]  Luciano Lavagno,et al.  Hardware and Petri Nets: Application to Asynchronous Circuit Design , 2000, ICATPN.

[43]  Robin Milner,et al.  On Observing Nondeterminism and Concurrency , 1980, ICALP.

[44]  Peter A. Beerel,et al.  Automatic gate-level synthesis of speed-independent circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[45]  Eby G. Friedman,et al.  System Timing , 2000, The VLSI Handbook.