论文信息 - A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique

A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique

A 6 b 500 MSample/s Flash ADC employs interpolated auto-zeroing carried out in background mode. To improve the ADC differential nonlinearity characteristic, a resistor network with its inherent error averaging property is employed for interpolation.

Kwangho Yoon | Sungkyung Park | Wonchan Kim

[1] S. Tsukamoto,et al. A CMOS 6b 400 M sample/s ADC with error correction , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).