Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs
暂无分享,去创建一个
Jun Tae Jang | Sung-Jin Choi | Dong Myong Kim | Dae Hwan Kim | Hagyoul Bae | Jungmin Lee | Jun Seok Hwang | Jaeyeop Ahn | Jinsoo Yoon
[1] D. Schroder. Semiconductor Material and Device Characterization , 1990 .
[2] D. M. Kim,et al. Modeling and extraction of gate bias-dependent parasitic source and drain resistances in MOSFETs , 2003 .
[3] Robert H. Dennard,et al. CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.
[4] Dong Myong Kim,et al. Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method , 2010, IEEE Electron Device Letters.
[5] Gerard Ghibaudo,et al. A New Technique to Extract the Source/Drain Series Resistance of MOSFETs , 2009, IEEE Electron Device Letters.
[6] Y.H. Chang,et al. A Simple Method to Extract Source/Drain Series Resistance for Advanced MOSFETs , 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.
[7] Sung-Jin Choi,et al. Dual-Sweep Combinational Transconductance Technique for Separate Extraction of Parasitic Resistances in Amorphous Thin-Film Transistors , 2015, IEEE Electron Device Letters.
[8] M.H. Seavey,et al. Source and drain resistance determination for MOSFET's , 1984, IEEE Electron Device Letters.
[9] D. Schroder. Semiconductor Material and Device Characterization, 3rd Edition , 2005 .
[10] K.K. Ng,et al. Analysis of the gate-voltage-dependent series resistance of MOSFET's , 1986, IEEE Transactions on Electron Devices.
[11] Daniel Mathiot,et al. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs , 2002 .
[12] Dong Myong Kim,et al. Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs , 2011, IEEE Electron Device Letters.
[13] G.J. Hu,et al. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's , 1987, IEEE Transactions on Electron Devices.
[14] R. Shrivastava,et al. A simple model for the overlap capacitance of a VLSI MOS device , 1982, IEEE Transactions on Electron Devices.