Modeling and Separate Extraction Technique for Gate Bias-Dependent Parasitic Resistances and Overlap Length in MOSFETs

We report a technique for separate extraction of extrinsic source/drain (S/D) resistances (R<sub>Se</sub>/R<sub>De</sub>) and gate bias (V<sub>GS</sub>)-dependent but channel length (L)-independent intrinsic source/drain (R<sub>Si</sub>/R<sub>Di</sub>) resistances for the overlap region in MOSFETs. For extraction of the overlap length (L<sub>ov</sub>) in the heavily doped S/D regions, an analytical capacitance model for the depletion region is employed with the gate-to-source and gate-to-drain capacitance-voltage (C<sub>G-S</sub>, C<sub>G-D</sub>) characteristics. After verifying the extracted overlap length through a 2-D technology computer-aided design simulation, we successfully extract V<sub>GS</sub>-dependent R<sub>Si</sub> = 0.9~3.7 Ω and R<sub>Di</sub> = 1.0~3.9 Ω in an n-channel MOSFET with W = 140 μm and L = 0.35 μm. In addition, V<sub>GS</sub>- and L-independent extrinsic S/D resistances are separately extracted to be R<sub>Se</sub> = 5.1 Ω and R<sub>De</sub> = 5.0 Ω, respectively.

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