Efficient VLSI design for SIFT feature description

The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipelining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13µm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.

[1]  Chyi-Yeu Lin,et al.  Multi-Functional Intelligent Robot DOC-2 , 2006, 2006 6th IEEE-RAS International Conference on Humanoid Robots.

[2]  Cordelia Schmid,et al.  Scale & Affine Invariant Interest Point Detectors , 2004, International Journal of Computer Vision.

[3]  Satoru Yamamoto,et al.  Systolic Architecture for Computational Fluid Dynamics on FPGAs , 2007 .

[4]  Matthijs C. Dorst Distinctive Image Features from Scale-Invariant Keypoints , 2011 .

[5]  Keith Redmill,et al.  Systems for Safety and Autonomous Behavior in Cars: The DARPA Grand Challenge Experience , 2007, Proceedings of the IEEE.

[6]  Takeshi Ikenaga,et al.  A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT , 2009, 2009 Fifth International Joint Conference on INC, IMS and IDC.

[7]  G LoweDavid,et al.  Distinctive Image Features from Scale-Invariant Keypoints , 2004 .

[8]  Karsten Berns,et al.  Hardware/Software co-design of a key point detector on FPGA , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[9]  George A. Constantinides,et al.  A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection , 2008, IEEE Transactions on Circuits and Systems for Video Technology.

[10]  Takeshi Ikenaga,et al.  An FPGA-Based Real-Time Hardware Accelerator for Orientation Calculation Part in SIFT , 2009, 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing.

[11]  Wenquan Feng,et al.  An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher , 2009, 2009 International Conference on Field-Programmable Technology.

[12]  W. Eric L. Grimson,et al.  Learning Patterns of Activity Using Real-Time Tracking , 2000, IEEE Trans. Pattern Anal. Mach. Intell..

[13]  Donghyun Kim,et al.  81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Christophe Bobda,et al.  Optimizing Logarithmic Arithmetic on FPGAs , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).