Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems

[1]  M. Watts,et al.  Ultralow power silicon microdisk modulators and switches , 2008, 2008 5th IEEE International Conference on Group IV Photonics.

[2]  M. Lipson,et al.  CMOS-compatible athermal silicon microring resonators. , 2009, Optics express.

[3]  K. Bergman,et al.  Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications , 2008, LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society.

[4]  Leonid Oliker,et al.  Energy-Efficient Computing for Extreme-Scale Science , 2009, Computer.

[5]  Leonid Oliker,et al.  Science-driven system architecture: A new process for leadership class computing , 2004 .

[6]  Leonid Oliker,et al.  Integrated performance monitoring of a cosmology application on leading HEC platforms , 2005, 2005 International Conference on Parallel Processing (ICPP'05).

[7]  D.A.B. Miller,et al.  Rationale and challenges for optical interconnects to electronic chips , 2000, Proceedings of the IEEE.

[8]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[9]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[10]  T. Cinkler,et al.  Multi-layer traffic engineering schemes in GMPLS networks , 2005, Proceedings of 2005 7th International Conference Transparent Optical Networks, 2005..

[11]  Raymond P. LeBeau,et al.  High-Cost CFD on a Low-Cost Cluster , 2000, ACM/IEEE SC 2000 Conference (SC'00).

[12]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[13]  James Demmel,et al.  SuperLU_DIST: A scalable distributed-memory sparse direct solver for unsymmetric linear systems , 2003, TOMS.

[14]  Pradeep Dubey,et al.  Larrabee: A Many-Core x86 Architecture for Visual Computing , 2009, IEEE Micro.

[15]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[16]  Luca P. Carloni,et al.  Design Exploration of Optical Interconnection Networks for Chip Multiprocessors , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[17]  Jeffrey S. Vetter,et al.  Communication characteristics of large-scale scientific applications for contemporary cluster architectures , 2002, Proceedings 16th International Parallel and Distributed Processing Symposium.

[18]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[19]  K. Bergman,et al.  High-Speed 2×2 switch for multi-wavelength message routing in on-chip silicon photonic networks , 2008, 2008 34th European Conference on Optical Communication.

[20]  Leonid Oliker,et al.  Silicon Nanophotonic Network-on-Chip Using TDM Arbitration , 2010, 2010 18th IEEE Symposium on High Performance Interconnects.

[21]  Leonid Oliker,et al.  Scientific Application Performance on Candidate PetaScale Platforms , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[22]  Ian O'Connor,et al.  Heterogeneous modelling of an optical network-on-chip with SystemC , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[23]  Jeffrey S. Vetter,et al.  An Empirical Performance Evaluation of Scalable Scientific Applications , 2002, ACM/IEEE SC 2002 Conference (SC'02).

[24]  William J. Dally,et al.  Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.

[25]  Leonid Oliker,et al.  Reconfigurable hybrid interconnection for static and dynamic scientific applications , 2007, CF '07.

[26]  David A. B. Miller,et al.  Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture , 1997, J. Parallel Distributed Comput..

[27]  Christopher Batten,et al.  Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics , 2008, 2008 16th IEEE Symposium on High Performance Interconnects.

[28]  Ian O'Connor,et al.  Towards reconfigurable optical networks on chip , 2005, ReCoSoC.

[29]  Vipul Gupta,et al.  Performance analysis of a synchronous, circuit-switched interconnection cached network , 1994, ICS '94.

[30]  Mark A. Franklin,et al.  Gemini: An Optical Interconnection Network for Parallel Processing , 2002, IEEE Trans. Parallel Distributed Syst..

[31]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[32]  Rolf Rabenseifner,et al.  Automatic Profiling of MPI Applications with Hardware Performance Counters , 1999, PVM/MPI.

[33]  Ronald P. Luijten,et al.  Optical-packet-switched interconnect for supercomputer applications[Invited] , 2004 .

[34]  José Duato,et al.  Adaptive bubble router: a design to improve performance in torus networks , 1999, Proceedings of the 1999 International Conference on Parallel Processing.

[35]  Lin-Wang Wang.  A survey of codes and algorithms used in NERSC material scienceallocations , 2006 .

[36]  Hans Eberle,et al.  Separated High-Bandwidth and Low-Latency Communication in the Cluster Interconnect Clint , 2002, ACM/IEEE SC 2002 Conference (SC'02).

[37]  F. Xia,et al.  High-throughput silicon nanophotonic wavelength-insensitive switch for on-chip optical networks , 2008 .

[38]  V. L. Rideout,et al.  Device design considerations for ion implanted n-channel MOSFETs , 1975 .

[39]  Philip G. Emma,et al.  Interconnects in the Third Dimension: Design Challenges for 3D ICs , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[40]  Mark Horowitz,et al.  High-speed electrical signaling: overview and limitations , 1998, IEEE Micro.

[41]  T. Hahm,et al.  Size Scaling of Turbulent Transport in Magnetically Confined Plasmas , 2002 .

[42]  W. Lee,et al.  Gyrokinetic Particle Simulation Model , 1987 .

[43]  Chak-Kuen Wong,et al.  Covering edges by cliques with regard to keyword conflicts and intersection graphs , 1978, CACM.

[44]  L. Smarr,et al.  The OptIPuter, Quartzite, and Starlight projects: a campus to global-scale testbed for optical technologies enabling LambdaGrid computing , 2005, OFC/NFOEC Technical Digest. Optical Fiber Communication Conference, 2005..

[45]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[46]  Joel Mambretti,et al.  Optical Switching Middleware for the OptlPuter , 2003 .

[47]  J. Qiang,et al.  A parallel particle-in-cell model for beam-beam interaction in high energy ring colliders , 2004 .

[48]  Luca P. Carloni,et al.  On the Design of a Photonic Network-on-Chip , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[49]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[50]  Lin-wang Wang,et al.  Parallel Empirical Pseudopotential Electronic Structure Calculations for Million Atom Systems , 2000 .

[51]  A. Varga,et al.  THE OMNET++ DISCRETE EVENT SIMULATION SYSTEM , 2003 .