Delay locked loop circuit

The present invention relates to a semiconductor design technology, in particular the delay-locked loop of a synchronous (Synchronous) DRAM: relates to (DLL Delay Locked Loop) circuit, more detail is the power-down mode for low-power (Low Power) operation of the semiconductor (Power Down Mode) in operation relates to a circuit for the stable operation of the delay lock loop (DLL) circuit. The present invention is in the power-down mode when entering may occur (Power down entry) phase update (Phase Update) as to prevent the interruption of the operation, indicating that the last period of the phase update (Phase Update) is until the clock signal is activated It gives delays the off (off) of the clock buffers. DLL, clock buffers, the power-down mode, the phase update, the precharge (PRE CHARGE), a clock buffer control