Disseminating critical target-specific synchronization information in parallel discrete event simulations

A hardware-based framework which supports a wide range of parallel discrete event synchronization protocols has been proposed in [Reyn92]. This framework offloads all synchronization activity from the host processors and host communication network in the system. The underlying hardware computes results of global, binary associative operations, or global reductions. In this paper we present results of simulations that strongly suggest the need for a next-generation reduction network which computes and disseminates results of target-specific reductions to support both aggressive and non-aggressive parallel discrete event simulations. Target-specific reductions allow a logical process to receive synchronization information only from those logical processes which may have a direct or indirect impact on its performance.

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