Hardware and Software for Approximate Computing
暂无分享,去创建一个
[1] Yu Wang,et al. RRAM-Based Analog Approximate Computing , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Jie Liu,et al. Scalable-effort classifiers for energy-efficient machine learning , 2015, DAC.
[3] Kia Bazargan,et al. Axilog: Language support for approximate hardware design , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[4] Jin Miao,et al. Modeling and synthesis of approximate digital circuits , 2014 .
[5] Alexander Aiken,et al. Stochastic optimization of floating-point programs with tunable precision , 2014, PLDI.
[6] K. McKinley,et al. Uncertain: a first-order type for uncertain data , 2014, ASPLOS.
[7] Kaushik Roy,et al. Quality programmable vector processors for approximate computing , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[8] Sarah Abdallah,et al. TABSH: Tag-based stochastic hardware , 2013, 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC).
[9] Sriram K. Rajamani,et al. Efficiently Sampling Probabilistic Programs via Program Analysis , 2013, AISTATS.
[10] Swarat Chaudhuri,et al. A Semantics for Approximate Program Transformations , 2013, ArXiv.
[11] Luis Ceze,et al. Neural Acceleration for General-Purpose Approximate Programs , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[12] Huawei Li,et al. SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change Memory in Video Applications via Approximate Write , 2012, 2012 IEEE 21st Asian Test Symposium.
[13] Vijayalakshmi Srinivasan,et al. Programming with relaxed synchronization , 2012, RACES '12.
[14] Michael Cohen,et al. Energy types , 2012, OOPSLA '12.
[15] Martin C. Rinard,et al. Proving acceptability properties of relaxed nondeterministic approximate programs , 2012, PLDI.
[16] Kaushik Roy,et al. SALSA: Systematic logic synthesis of approximate circuits , 2012, DAC Design Automation Conference 2012.
[17] A. Sebastian,et al. A Framework for Reliability Assessment in Multilevel Phase-Change Memory , 2012, 2012 4th IEEE International Memory Workshop.
[18] Elaine Shi,et al. GUPT: privacy preserving data analysis made easy , 2012, SIGMOD Conference.
[19] Onur Mutlu,et al. Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[20] Jun Yang,et al. Improving write operations in MLC phase change memory , 2012, IEEE International Symposium on High-Performance Comp Architecture.
[21] Wei Wu,et al. Optimizing NAND flash-based SSDs via retention relaxation , 2012, FAST.
[22] Huawei Li,et al. A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications , 2011, 2011 Asian Test Symposium.
[23] Kaushik Roy,et al. IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.
[24] Dan Grossman,et al. EnerJ: approximate data types for safe and general low-power computation , 2011, PLDI '11.
[25] Lingamneni Avinash,et al. Energy parsimonious circuit design through probabilistic pruning , 2011, 2011 Design, Automation & Test in Europe.
[26] A. J. Tack,et al. Mnemosyne: lightweight persistent memory , 2011, ASPLOS XVI.
[27] Rajesh K. Gupta,et al. NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories , 2011, ASPLOS XVI.
[28] Yue Wang,et al. Exploiting Half-Wits: Smarter Storage for Low-Power Devices , 2011, FAST.
[29] Rajesh K. Gupta,et al. Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[30] Haralampos Pozidis,et al. Multilevel phase-change memory , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.
[31] Benjamin C. Pierce,et al. Distance makes the types grow stronger: a calculus for differential privacy , 2010, ICFP '10.
[32] Guido Torelli,et al. Voltage-Driven Partial-RESET Multilevel Programming in Phase-Change Memories , 2010, IEEE Transactions on Electron Devices.
[33] Bill Bradley,et al. Low power logic for statistical inference , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).
[34] Shreesha Srinath,et al. Design and Implementation of an “Approximate” Communication System for Wireless Media Applications , 2010, IEEE/ACM Transactions on Networking.
[35] Moinuddin K. Qureshi,et al. Morphable memory system: a robust architecture for exploiting multi-level phase change memories , 2010, ISCA.
[36] Karin Strauss,et al. Use ECP, not ECC, for hard failures in resistive memories , 2010, ISCA.
[37] Andrew C. Myers,et al. A Semantic Framework for Declassification and Endorsement , 2010, ESOP.
[38] Douglas L. Jones,et al. Scalable stochastic processors , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[39] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[40] P. Stanley-Marbell,et al. Encoding efficiency of digital number representations under deviation constraints , 2009, 2009 IEEE Information Theory Workshop.
[41] Kevin Skadron,et al. Rodinia: A benchmark suite for heterogeneous computing , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).
[42] Vijayalakshmi Srinivasan,et al. Scalable high performance main memory system using phase-change memory technology , 2009, ISCA '09.
[43] Michael D. Ernst,et al. Practical pluggable types for java , 2008, ISSTA '08.
[44] Diana Franklin,et al. Efficient fault tolerance in multi-media applications through selective instruction replication , 2008, WREFT '08.
[45] Paul Chow,et al. Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy , 2008, TECS.
[46] Paolo Ienne,et al. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.
[47] Sarita V. Adve,et al. Understanding the propagation of hard errors to software and implications for resilient system design , 2008, ASPLOS.
[48] Hsien-Hsin S. Lee,et al. Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[49] Håkan L. S. Younes. Error Control for Probabilistic Model Checking , 2006, VMCAI.
[50] D. Burger,et al. Microprocessor pipeline energy analysis , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..
[51] Rob A. Rutenbar,et al. Reducing power by optimizing the necessary precision/range of floating-point arithmetic , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[52] Ken Takeuchi,et al. A multipage cell architecture for high-speed programming multilevel NAND flash memories , 1998, IEEE J. Solid State Circuits.
[53] Dexter Kozen,et al. Semantics of probabilistic programs , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).
[54] Mayur Naik,et al. Expectation-Oriented Framework for Automating Approximate Programming , 2013 .
[55] Kaushik Roy,et al. Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[56] Christian Bienia,et al. Benchmarking modern multiprocessors , 2011 .
[57] Animesh Kumar,et al. SRAM Leakage-Power Optimization Framework: a System Level Approach , 2008 .